diff --git a/boards/arm/mimxrt1024_evk/doc/index.rst b/boards/arm/mimxrt1024_evk/doc/index.rst index 11c5c948e81..e5fd0a3025f 100644 --- a/boards/arm/mimxrt1024_evk/doc/index.rst +++ b/boards/arm/mimxrt1024_evk/doc/index.rst @@ -97,6 +97,8 @@ features: +-----------+------------+-------------------------------------+ | DMA | on-chip | dma | +-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ The default configuration can be found in the defconfig file: ``boards/arm/mimxrt1024_evk/mimxrt1024_evk_defconfig`` @@ -151,6 +153,10 @@ The MIMXRT1024 SoC has five pairs of pinmux/gpio controllers. +---------------+-----------------+---------------------------+ | GPIO_SD_B1_03 | LPI2C4_SDA | I2C SDA | +---------------+-----------------+---------------------------+ +| GPIO_AD_B1_11 | ADC1 | ADC1 Channel 11 | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B1_10 | ADC1 | ADC1 Channel 10 | ++---------------+-----------------+---------------------------+ System Clock ============ diff --git a/boards/arm/mimxrt1024_evk/mimxrt1024_evk.dts b/boards/arm/mimxrt1024_evk/mimxrt1024_evk.dts index 2cf708e1ff2..db1ba5ae0bd 100644 --- a/boards/arm/mimxrt1024_evk/mimxrt1024_evk.dts +++ b/boards/arm/mimxrt1024_evk/mimxrt1024_evk.dts @@ -120,3 +120,7 @@ &lpspi1 { status = "okay"; }; + +&adc1 { + status = "okay"; +}; diff --git a/boards/arm/mimxrt1024_evk/mimxrt1024_evk.yaml b/boards/arm/mimxrt1024_evk/mimxrt1024_evk.yaml index 1742694c016..cb5de49be85 100644 --- a/boards/arm/mimxrt1024_evk/mimxrt1024_evk.yaml +++ b/boards/arm/mimxrt1024_evk/mimxrt1024_evk.yaml @@ -21,3 +21,4 @@ supported: - netif:eth - watchdog - spi + - adc diff --git a/boards/arm/mimxrt1024_evk/pinmux.c b/boards/arm/mimxrt1024_evk/pinmux.c index c20d05302e6..7567f92a411 100644 --- a/boards/arm/mimxrt1024_evk/pinmux.c +++ b/boards/arm/mimxrt1024_evk/pinmux.c @@ -147,6 +147,22 @@ static int mimxrt1024_evk_init(const struct device *dev) IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | IOMUXC_SW_PAD_CTL_PAD_DSE(6)); #endif +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(adc1), okay) && CONFIG_ADC + /* ADC1 Channel 10 and 11 are on pins 2 and 4 of J18 */ + /* ADC1 Channel 10 */ + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_10_GPIO1_IO26, 0U); + /* ADC1 Channel 11 */ + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_11_GPIO1_IO27, 0U); + + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_10_GPIO1_IO26, + IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | + IOMUXC_SW_PAD_CTL_PAD_DSE(6)); + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_11_GPIO1_IO27, + IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | + IOMUXC_SW_PAD_CTL_PAD_DSE(6)); + #endif return 0; diff --git a/samples/drivers/adc/boards/mimxrt1024_evk.overlay b/samples/drivers/adc/boards/mimxrt1024_evk.overlay new file mode 100644 index 00000000000..cecde8e2cb0 --- /dev/null +++ b/samples/drivers/adc/boards/mimxrt1024_evk.overlay @@ -0,0 +1,12 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2021 NXP + */ + +/ { + zephyr,user { + /* adjust channel number according to pinmux in board.dts */ + io-channels = <&adc1 10>; + }; +}; diff --git a/tests/drivers/adc/adc_api/src/test_adc.c b/tests/drivers/adc/adc_api/src/test_adc.c index 0000a897d64..3de3e2736d2 100644 --- a/tests/drivers/adc/adc_api/src/test_adc.c +++ b/tests/drivers/adc/adc_api/src/test_adc.c @@ -298,7 +298,8 @@ #elif defined(CONFIG_BOARD_MIMXRT1050_EVK) || \ defined(CONFIG_BOARD_MIMXRT1050_EVK_QSPI) || \ defined(CONFIG_BOARD_MIMXRT1064_EVK) || \ - defined(CONFIG_BOARD_MIMXRT1060_EVK) + defined(CONFIG_BOARD_MIMXRT1060_EVK) || \ + defined(CONFIG_BOARD_MIMXRT1024_EVK) #define ADC_DEVICE_NAME DT_LABEL(DT_INST(0, nxp_mcux_12b1msps_sar)) #define ADC_RESOLUTION 12 #define ADC_GAIN ADC_GAIN_1