drivers: flash: Introduce i.MX RT FlexSPI driver
Introduces a new flash driver for the FlexSPI peripheral on i.MX RT SoCs. The hardware provides a flexible sequence engine (LUT) that supports various types of external devices, including serial NOR flash, serial NAND flash, HyperBus (HyperFlash/HyperRAM), and FPGAs. It supports up to four connected devices in single/dual/quad/octal modes and provides memory-mapped read/write access to these devices through the AHB bus. The driver implementation consists of a shared controller for each FlexSPI peripheral instance, and protocol-specific device drivers for each external device. The controller provides a private interface for multiple devices to access the FlexSPI peripheral registers. FlexSPI devices provide the public flash driver interface to applications or subsystems like storage or flash file systems; they also provide protocol-specific LUT sequences to the controller. Currently the only device type supported is QSPI NOR flash, but other types like HyperFlash will be added later. XIP is not yet supported, as this requires additional work to relocate code to RAM and managing interrupts. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
This commit is contained in:
Maureen Helm
Anas Nashif
parent
52b77ac956
commit
b0bd5a6ece
6 changed files with 693 additions and 1 deletions
507
drivers/flash/flash_mcux_flexspi_nor.c
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507
drivers/flash/flash_mcux_flexspi_nor.c
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@ -0,0 +1,507 @@
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/*
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* Copyright 2020 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nxp_imx_flexspi_nor
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#include <drivers/flash.h>
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#include <logging/log.h>
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#include <sys/util.h>
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#include "spi_nor.h"
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#include "flash_mcux_flexspi.h"
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#ifdef CONFIG_HAS_MCUX_CACHE
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#include <fsl_cache.h>
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#endif
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#define NOR_WRITE_SIZE 1
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#define NOR_ERASE_VALUE 0xff
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LOG_MODULE_DECLARE(flash_flexspi, CONFIG_FLASH_LOG_LEVEL);
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enum {
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/* SPI instructions */
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READ_ID,
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READ_STATUS_REG,
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WRITE_STATUS_REG,
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WRITE_ENABLE,
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ERASE_SECTOR,
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ERASE_CHIP,
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/* Quad SPI instructions */
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READ_FAST_QUAD_OUTPUT,
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PAGE_PROGRAM_QUAD_INPUT,
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ENTER_QPI,
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};
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struct flash_flexspi_nor_config {
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char *controller_label;
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flexspi_port_t port;
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flexspi_device_config_t config;
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struct flash_pages_layout layout;
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struct flash_parameters flash_parameters;
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};
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struct flash_flexspi_nor_data {
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const struct device *controller;
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};
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static const uint32_t flash_flexspi_nor_lut[][4] = {
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[READ_ID] = {
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_RDID,
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kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04),
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},
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[READ_STATUS_REG] = {
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_RDSR,
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kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04),
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},
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[WRITE_STATUS_REG] = {
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_WRSR,
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kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x04),
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},
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[WRITE_ENABLE] = {
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_WREN,
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kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
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},
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[ERASE_SECTOR] = {
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_SE,
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kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18),
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},
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[ERASE_CHIP] = {
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_CE,
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kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
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},
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[READ_FAST_QUAD_OUTPUT] = {
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x6B,
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kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18),
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_4PAD, 0x08,
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kFLEXSPI_Command_READ_SDR, kFLEXSPI_4PAD, 0x04),
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},
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[PAGE_PROGRAM_QUAD_INPUT] = {
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x32,
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kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18),
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_4PAD, 0x04,
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kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
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},
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[ENTER_QPI] = {
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x35,
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kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
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},
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};
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static int flash_flexspi_nor_get_vendor_id(const struct device *dev,
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uint8_t *vendor_id)
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{
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const struct flash_flexspi_nor_config *config = dev->config;
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struct flash_flexspi_nor_data *data = dev->data;
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uint32_t buffer = 0;
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int ret;
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flexspi_transfer_t transfer = {
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.deviceAddress = 0,
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.port = config->port,
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.cmdType = kFLEXSPI_Read,
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.SeqNumber = 1,
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.seqIndex = READ_ID,
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.data = &buffer,
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.dataSize = 1,
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};
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LOG_DBG("Reading id");
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ret = flash_flexspi_transfer(data->controller, &transfer);
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*vendor_id = buffer;
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return ret;
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}
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static int flash_flexspi_nor_read_status(const struct device *dev,
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uint32_t *status)
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{
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const struct flash_flexspi_nor_config *config = dev->config;
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struct flash_flexspi_nor_data *data = dev->data;
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flexspi_transfer_t transfer = {
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.deviceAddress = 0,
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.port = config->port,
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.cmdType = kFLEXSPI_Read,
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.SeqNumber = 1,
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.seqIndex = READ_STATUS_REG,
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.data = status,
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.dataSize = 1,
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};
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LOG_DBG("Reading status register");
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return flash_flexspi_transfer(data->controller, &transfer);
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}
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static int flash_flexspi_nor_write_status(const struct device *dev,
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uint32_t *status)
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{
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const struct flash_flexspi_nor_config *config = dev->config;
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struct flash_flexspi_nor_data *data = dev->data;
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flexspi_transfer_t transfer = {
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.deviceAddress = 0,
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.port = config->port,
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.cmdType = kFLEXSPI_Write,
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.SeqNumber = 1,
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.seqIndex = WRITE_STATUS_REG,
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.data = status,
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.dataSize = 1,
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};
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LOG_DBG("Writing status register");
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return flash_flexspi_transfer(data->controller, &transfer);
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}
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static int flash_flexspi_nor_write_enable(const struct device *dev)
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{
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const struct flash_flexspi_nor_config *config = dev->config;
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struct flash_flexspi_nor_data *data = dev->data;
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flexspi_transfer_t transfer = {
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.deviceAddress = 0,
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.port = config->port,
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.cmdType = kFLEXSPI_Command,
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.SeqNumber = 1,
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.seqIndex = WRITE_ENABLE,
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.data = NULL,
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.dataSize = 0,
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};
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LOG_DBG("Enabling write");
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return flash_flexspi_transfer(data->controller, &transfer);
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}
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static int flash_flexspi_nor_erase_sector(const struct device *dev,
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off_t offset)
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{
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const struct flash_flexspi_nor_config *config = dev->config;
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struct flash_flexspi_nor_data *data = dev->data;
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flexspi_transfer_t transfer = {
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.deviceAddress = offset,
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.port = config->port,
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.cmdType = kFLEXSPI_Command,
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.SeqNumber = 1,
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.seqIndex = ERASE_SECTOR,
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.data = NULL,
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.dataSize = 0,
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};
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LOG_DBG("Erasing sector at 0x%08x", offset);
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return flash_flexspi_transfer(data->controller, &transfer);
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}
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static int flash_flexspi_nor_erase_chip(const struct device *dev)
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{
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const struct flash_flexspi_nor_config *config = dev->config;
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struct flash_flexspi_nor_data *data = dev->data;
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flexspi_transfer_t transfer = {
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.deviceAddress = 0,
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.port = config->port,
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.cmdType = kFLEXSPI_Command,
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.SeqNumber = 1,
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.seqIndex = ERASE_CHIP,
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.data = NULL,
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.dataSize = 0,
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};
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LOG_DBG("Erasing chip");
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return flash_flexspi_transfer(data->controller, &transfer);
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}
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static int flash_flexspi_nor_page_program(const struct device *dev,
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off_t offset, const void *buffer, size_t len)
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{
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const struct flash_flexspi_nor_config *config = dev->config;
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struct flash_flexspi_nor_data *data = dev->data;
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flexspi_transfer_t transfer = {
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.deviceAddress = offset,
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.port = config->port,
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.cmdType = kFLEXSPI_Write,
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.SeqNumber = 1,
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.seqIndex = PAGE_PROGRAM_QUAD_INPUT,
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.data = (uint32_t *) buffer,
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.dataSize = len,
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};
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LOG_DBG("Page programming %d bytes to 0x%08x", len, offset);
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return flash_flexspi_transfer(data->controller, &transfer);
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}
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static int flash_flexspi_nor_wait_bus_busy(const struct device *dev)
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{
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uint32_t status = 0;
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int ret;
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do {
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ret = flash_flexspi_nor_read_status(dev, &status);
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LOG_DBG("status: 0x%x", status);
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if (ret) {
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LOG_ERR("Could not read status");
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return ret;
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}
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} while (status & BIT(0));
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return 0;
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}
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static int flash_flexspi_nor_enable_quad_mode(const struct device *dev)
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{
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struct flash_flexspi_nor_data *data = dev->data;
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uint32_t status = 0x40;
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flash_flexspi_nor_write_status(dev, &status);
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flash_flexspi_nor_wait_bus_busy(dev);
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flash_flexspi_reset(data->controller);
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return 0;
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}
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static int flash_flexspi_nor_read(const struct device *dev, off_t offset,
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void *buffer, size_t len)
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{
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const struct flash_flexspi_nor_config *config = dev->config;
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struct flash_flexspi_nor_data *data = dev->data;
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uint8_t *src = flash_flexspi_get_ahb_address(data->controller,
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config->port,
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offset);
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memcpy(buffer, src, len);
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return 0;
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}
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static int flash_flexspi_nor_write(const struct device *dev, off_t offset,
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const void *buffer, size_t len)
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{
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const struct flash_flexspi_nor_config *config = dev->config;
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struct flash_flexspi_nor_data *data = dev->data;
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size_t size = len;
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uint8_t *src = (uint8_t *) buffer;
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int i;
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uint8_t *dst = flash_flexspi_get_ahb_address(data->controller,
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config->port,
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offset);
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while (len) {
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i = MIN(SPI_NOR_PAGE_SIZE, len);
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flash_flexspi_nor_write_enable(dev);
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flash_flexspi_nor_page_program(dev, offset, src, i);
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flash_flexspi_nor_wait_bus_busy(dev);
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flash_flexspi_reset(data->controller);
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offset += i;
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len -= i;
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}
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#ifdef CONFIG_HAS_MCUX_CACHE
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DCACHE_InvalidateByRange((uint32_t) dst, size);
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#endif
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return 0;
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}
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static int flash_flexspi_nor_erase(const struct device *dev, off_t offset,
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size_t size)
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{
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const struct flash_flexspi_nor_config *config = dev->config;
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struct flash_flexspi_nor_data *data = dev->data;
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int num_sectors = size / SPI_NOR_SECTOR_SIZE;
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int i;
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uint8_t *dst = flash_flexspi_get_ahb_address(data->controller,
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config->port,
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offset);
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if (offset % SPI_NOR_SECTOR_SIZE) {
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LOG_ERR("Invalid offset");
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return -EINVAL;
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}
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if (size % SPI_NOR_SECTOR_SIZE) {
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LOG_ERR("Invalid size");
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return -EINVAL;
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}
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if ((offset == 0) && (size == config->config.flashSize * KB(1))) {
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flash_flexspi_nor_write_enable(dev);
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flash_flexspi_nor_erase_chip(dev);
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flash_flexspi_nor_wait_bus_busy(dev);
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flash_flexspi_reset(data->controller);
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} else {
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for (i = 0; i < num_sectors; i++) {
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flash_flexspi_nor_write_enable(dev);
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flash_flexspi_nor_erase_sector(dev, offset);
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flash_flexspi_nor_wait_bus_busy(dev);
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flash_flexspi_reset(data->controller);
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offset += SPI_NOR_SECTOR_SIZE;
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}
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}
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#ifdef CONFIG_HAS_MCUX_CACHE
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DCACHE_InvalidateByRange((uint32_t) dst, size);
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#endif
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return 0;
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}
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static int flash_flexspi_nor_write_protection(const struct device *dev,
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bool enable)
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{
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return 0;
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}
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static const struct flash_parameters *flash_flexspi_nor_get_parameters(
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const struct device *dev)
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{
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const struct flash_flexspi_nor_config *config = dev->config;
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return &config->flash_parameters;
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}
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#if defined(CONFIG_FLASH_PAGE_LAYOUT)
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static void flash_flexspi_nor_pages_layout(const struct device *dev,
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const struct flash_pages_layout **layout, size_t *layout_size)
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{
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const struct flash_flexspi_nor_config *config = dev->config;
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*layout = &config->layout;
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*layout_size = 1;
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}
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#endif /* CONFIG_FLASH_PAGE_LAYOUT */
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static int flash_flexspi_nor_init(const struct device *dev)
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{
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const struct flash_flexspi_nor_config *config = dev->config;
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struct flash_flexspi_nor_data *data = dev->data;
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uint8_t vendor_id;
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data->controller = device_get_binding(config->controller_label);
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if (data->controller == NULL) {
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LOG_ERR("Could not find controller");
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return -EINVAL;
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}
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if (flash_flexspi_set_flash_config(data->controller, &config->config,
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config->port)) {
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LOG_ERR("Could not set flash configuration");
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return -EINVAL;
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}
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if (flash_flexspi_update_lut(data->controller, 0,
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(const uint32_t *) flash_flexspi_nor_lut,
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sizeof(flash_flexspi_nor_lut) / 4)) {
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LOG_ERR("Could not update lut");
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return -EINVAL;
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}
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flash_flexspi_reset(data->controller);
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if (flash_flexspi_nor_get_vendor_id(dev, &vendor_id)) {
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LOG_ERR("Could not read vendor id");
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return -EIO;
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}
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LOG_DBG("Vendor id: 0x%0x", vendor_id);
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if (flash_flexspi_nor_enable_quad_mode(dev)) {
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LOG_ERR("Could not enable quad mode");
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return -EIO;
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}
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return 0;
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}
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static const struct flash_driver_api flash_flexspi_nor_api = {
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.write_protection = flash_flexspi_nor_write_protection,
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.erase = flash_flexspi_nor_erase,
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.write = flash_flexspi_nor_write,
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.read = flash_flexspi_nor_read,
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.get_parameters = flash_flexspi_nor_get_parameters,
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#if defined(CONFIG_FLASH_PAGE_LAYOUT)
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.page_layout = flash_flexspi_nor_pages_layout,
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#endif
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};
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#define CONCAT3(x, y, z) x ## y ## z
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#define CS_INTERVAL_UNIT(unit) \
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CONCAT3(kFLEXSPI_CsIntervalUnit, unit, SckCycle)
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#define AHB_WRITE_WAIT_UNIT(unit) \
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CONCAT3(kFLEXSPI_AhbWriteWaitUnit, unit, AhbCycle)
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#define FLASH_FLEXSPI_DEVICE_CONFIG(n) \
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{ \
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.flexspiRootClk = MHZ(120), \
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.flashSize = DT_INST_PROP(n, size) / 8 / KB(1), \
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.CSIntervalUnit = \
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CS_INTERVAL_UNIT( \
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DT_INST_PROP(n, cs_interval_unit)), \
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.CSInterval = DT_INST_PROP(n, cs_interval), \
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.CSHoldTime = DT_INST_PROP(n, cs_hold_time), \
|
||||
.CSSetupTime = DT_INST_PROP(n, cs_setup_time), \
|
||||
.dataValidTime = DT_INST_PROP(n, data_valid_time), \
|
||||
.columnspace = DT_INST_PROP(n, column_space), \
|
||||
.enableWordAddress = DT_INST_PROP(n, word_addressable), \
|
||||
.AWRSeqIndex = 0, \
|
||||
.AWRSeqNumber = 0, \
|
||||
.ARDSeqIndex = READ_FAST_QUAD_OUTPUT, \
|
||||
.ARDSeqNumber = 1, \
|
||||
.AHBWriteWaitUnit = \
|
||||
AHB_WRITE_WAIT_UNIT( \
|
||||
DT_INST_PROP(n, ahb_write_wait_unit)), \
|
||||
.AHBWriteWaitInterval = \
|
||||
DT_INST_PROP(n, ahb_write_wait_interval), \
|
||||
} \
|
||||
|
||||
#define FLASH_FLEXSPI_NOR(n) \
|
||||
static const struct flash_flexspi_nor_config \
|
||||
flash_flexspi_nor_config_##n = { \
|
||||
.controller_label = DT_INST_BUS_LABEL(n), \
|
||||
.port = DT_INST_REG_ADDR(n), \
|
||||
.config = FLASH_FLEXSPI_DEVICE_CONFIG(n), \
|
||||
.layout = { \
|
||||
.pages_count = DT_INST_PROP(n, size) / 8 \
|
||||
/ SPI_NOR_SECTOR_SIZE, \
|
||||
.pages_size = SPI_NOR_SECTOR_SIZE, \
|
||||
}, \
|
||||
.flash_parameters = { \
|
||||
.write_block_size = NOR_WRITE_SIZE, \
|
||||
.erase_value = NOR_ERASE_VALUE, \
|
||||
}, \
|
||||
}; \
|
||||
\
|
||||
static struct flash_flexspi_nor_data \
|
||||
flash_flexspi_nor_data_##n; \
|
||||
\
|
||||
DEVICE_DT_INST_DEFINE(n, \
|
||||
flash_flexspi_nor_init, \
|
||||
device_pm_control_nop, \
|
||||
&flash_flexspi_nor_data_##n, \
|
||||
&flash_flexspi_nor_config_##n, \
|
||||
POST_KERNEL, \
|
||||
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
|
||||
&flash_flexspi_nor_api);
|
||||
|
||||
DT_INST_FOREACH_STATUS_OKAY(FLASH_FLEXSPI_NOR)
|
||||
Loading…
Add table
Add a link
Reference in a new issue