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drivers: dai/dmic: Add support for ace30 (PTL)

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Add dmic support in PTL.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
This commit is contained in:
Jaroslaw Stelter 2022-10-21 09:07:41 +02:00 • committed by Henrik Brix Andersen
commit b0abe57bc5
2 changed files with 9 additions and 9 deletions
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16
drivers/dai/intel/dmic/dmic.c
View file

@ -159,7 +159,7 @@ static inline void dai_dmic_release_ownership(const struct dai_intel_dmic *dmic)
static inline uint32_t dai_dmic_base(const struct dai_intel_dmic *dmic) static inline uint32_t dai_dmic_base(const struct dai_intel_dmic *dmic)
{ {
#ifdef CONFIG_SOC_INTEL_ACE20_LNL #if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30_PTL)
return dmic->hdamldmic_base; return dmic->hdamldmic_base;
#else #else
return dmic->shim_base; return dmic->shim_base;
@ -172,7 +172,7 @@ static inline void dai_dmic_set_sync_period(uint32_t period, const struct dai_in
uint32_t val = CONFIG_DAI_DMIC_HW_IOCLK / period - 1; uint32_t val = CONFIG_DAI_DMIC_HW_IOCLK / period - 1;
uint32_t base = dai_dmic_base(dmic); uint32_t base = dai_dmic_base(dmic);
/* DMIC Change sync period */ /* DMIC Change sync period */
#ifdef CONFIG_SOC_INTEL_ACE20_LNL #if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30_PTL)
sys_write32(sys_read32(base + DMICSYNC_OFFSET) | FIELD_PREP(DMICSYNC_SYNCPRD, val), sys_write32(sys_read32(base + DMICSYNC_OFFSET) | FIELD_PREP(DMICSYNC_SYNCPRD, val),
base + DMICSYNC_OFFSET); base + DMICSYNC_OFFSET);
sys_write32(sys_read32(base + DMICSYNC_OFFSET) | DMICSYNC_SYNCPU, sys_write32(sys_read32(base + DMICSYNC_OFFSET) | DMICSYNC_SYNCPU,
@ -286,7 +286,7 @@ static void dai_dmic_irq_handler(const void *data)
static inline void dai_dmic_dis_clk_gating(const struct dai_intel_dmic *dmic) static inline void dai_dmic_dis_clk_gating(const struct dai_intel_dmic *dmic)
{ {
/* Disable DMIC clock gating */ /* Disable DMIC clock gating */
#ifdef CONFIG_SOC_INTEL_ACE20_LNL /* Ace 2.0 */ #if (CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30_PTL)
sys_write32((sys_read32(dmic->vshim_base + DMICLVSCTL_OFFSET) | DMICLVSCTL_DCGD), sys_write32((sys_read32(dmic->vshim_base + DMICLVSCTL_OFFSET) | DMICLVSCTL_DCGD),
dmic->vshim_base + DMICLVSCTL_OFFSET); dmic->vshim_base + DMICLVSCTL_OFFSET);
#else #else
@ -298,10 +298,10 @@ static inline void dai_dmic_dis_clk_gating(const struct dai_intel_dmic *dmic)
static inline void dai_dmic_en_clk_gating(const struct dai_intel_dmic *dmic) static inline void dai_dmic_en_clk_gating(const struct dai_intel_dmic *dmic)
{ {
/* Enable DMIC clock gating */ /* Enable DMIC clock gating */
#ifdef CONFIG_SOC_INTEL_ACE20_LNL /* Ace 2.0 */ #if (CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30_PTL)
sys_write32((sys_read32(dmic->vshim_base + DMICLVSCTL_OFFSET) & ~DMICLVSCTL_DCGD), sys_write32((sys_read32(dmic->vshim_base + DMICLVSCTL_OFFSET) & ~DMICLVSCTL_DCGD),
dmic->vshim_base + DMICLVSCTL_OFFSET); dmic->vshim_base + DMICLVSCTL_OFFSET);
#else #else /* All other CAVS and ACE platforms */
sys_write32((sys_read32(dmic->shim_base + DMICLCTL_OFFSET) & ~DMICLCTL_DCGD), sys_write32((sys_read32(dmic->shim_base + DMICLCTL_OFFSET) & ~DMICLCTL_DCGD),
dmic->shim_base + DMICLCTL_OFFSET); dmic->shim_base + DMICLCTL_OFFSET);
#endif #endif
@ -312,7 +312,7 @@ static inline void dai_dmic_program_channel_map(const struct dai_intel_dmic *dmi
const struct dai_config *cfg, const struct dai_config *cfg,
uint32_t index) uint32_t index)
{ {
#ifdef CONFIG_SOC_INTEL_ACE20_LNL #if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30_PTL)
uint16_t pcmsycm = cfg->link_config; uint16_t pcmsycm = cfg->link_config;
uint32_t reg_add = dmic->shim_base + DMICXPCMSyCM_OFFSET + 0x0004*index; uint32_t reg_add = dmic->shim_base + DMICXPCMSyCM_OFFSET + 0x0004*index;
@ -321,7 +321,7 @@ static inline void dai_dmic_program_channel_map(const struct dai_intel_dmic *dmi
ARG_UNUSED(dmic); ARG_UNUSED(dmic);
ARG_UNUSED(cfg); ARG_UNUSED(cfg);
ARG_UNUSED(index); ARG_UNUSED(index);
#endif /* defined(CONFIG_SOC_INTEL_ACE20_LNL) */ #endif /* defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30_PTL) */
} }
static inline void dai_dmic_en_power(const struct dai_intel_dmic *dmic) static inline void dai_dmic_en_power(const struct dai_intel_dmic *dmic)
@ -331,7 +331,7 @@ static inline void dai_dmic_en_power(const struct dai_intel_dmic *dmic)
sys_write32((sys_read32(base + DMICLCTL_OFFSET) | DMICLCTL_SPA), sys_write32((sys_read32(base + DMICLCTL_OFFSET) | DMICLCTL_SPA),
base + DMICLCTL_OFFSET); base + DMICLCTL_OFFSET);
#ifdef CONFIG_SOC_INTEL_ACE20_LNL /* Ace 2.0 */ #if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30_PTL)
while (!(sys_read32(base + DMICLCTL_OFFSET) & DMICLCTL_CPA)) { while (!(sys_read32(base + DMICLCTL_OFFSET) & DMICLCTL_CPA)) {
k_sleep(K_USEC(100)); k_sleep(K_USEC(100));
} }

2
drivers/dai/intel/dmic/dmic.h
View file

@ -173,7 +173,7 @@ struct dai_intel_dmic {
/* hardware parameters */ /* hardware parameters */
uint32_t reg_base; uint32_t reg_base;
uint32_t shim_base; uint32_t shim_base;
#ifdef CONFIG_SOC_INTEL_ACE20_LNL #if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30_PTL)
uint32_t hdamldmic_base; uint32_t hdamldmic_base;
uint32_t vshim_base; uint32_t vshim_base;
#endif #endif