diff --git a/drivers/adc/adc_stm32.c b/drivers/adc/adc_stm32.c
index 59057ceca03..da8511bbec8 100644
--- a/drivers/adc/adc_stm32.c
+++ b/drivers/adc/adc_stm32.c
@@ -148,7 +148,8 @@ static const u32_t table_samp_time[] = {
 	SMP_TIME(160, S_5),
 };
 #elif defined(CONFIG_SOC_SERIES_STM32L4X) || \
-	defined(CONFIG_SOC_SERIES_STM32WBX)
+	defined(CONFIG_SOC_SERIES_STM32WBX) || \
+	defined(CONFIG_SOC_SERIES_STM32G4X)
 static const u16_t acq_time_tbl[8] = {3, 7, 13, 25, 48, 93, 248, 641};
 static const u32_t table_samp_time[] = {
 	SMP_TIME(2,   S_5),
@@ -218,7 +219,8 @@ static void adc_stm32_start_conversion(struct device *dev)
 	defined(CONFIG_SOC_SERIES_STM32F3X) || \
 	defined(CONFIG_SOC_SERIES_STM32L0X) || \
 	defined(CONFIG_SOC_SERIES_STM32L4X) || \
-	defined(CONFIG_SOC_SERIES_STM32WBX)
+	defined(CONFIG_SOC_SERIES_STM32WBX) || \
+	defined(CONFIG_SOC_SERIES_STM32G4X)
 	LL_ADC_REG_StartConversion(adc);
 #else
 	LL_ADC_REG_StartConversionSWStart(adc);
@@ -282,7 +284,8 @@ static int start_read(struct device *dev, const struct adc_sequence *sequence)
 	defined(CONFIG_SOC_SERIES_STM32F3X) || \
 	defined(CONFIG_SOC_SERIES_STM32L0X) || \
 	defined(CONFIG_SOC_SERIES_STM32L4X) || \
-	defined(CONFIG_SOC_SERIES_STM32WBX)
+	defined(CONFIG_SOC_SERIES_STM32WBX) || \
+	defined(CONFIG_SOC_SERIES_STM32G4X)
 	LL_ADC_EnableIT_EOC(adc);
 #elif defined(CONFIG_SOC_SERIES_STM32F1X)
 	LL_ADC_EnableIT_EOS(adc);
@@ -458,7 +461,8 @@ static void adc_stm32_calib(struct device *dev)
 
 #if defined(CONFIG_SOC_SERIES_STM32F3X) || \
 	defined(CONFIG_SOC_SERIES_STM32L4X) || \
-	defined(CONFIG_SOC_SERIES_STM32WBX)
+	defined(CONFIG_SOC_SERIES_STM32WBX) || \
+	defined(CONFIG_SOC_SERIES_STM32G4X)
 	LL_ADC_StartCalibration(adc, LL_ADC_SINGLE_ENDED);
 #elif defined(CONFIG_SOC_SERIES_STM32F0X) || \
 	defined(CONFIG_SOC_SERIES_STM32L0X)
@@ -496,21 +500,23 @@ static int adc_stm32_init(struct device *dev)
 	}
 
 #if defined(CONFIG_SOC_SERIES_STM32L4X) || \
-	defined(CONFIG_SOC_SERIES_STM32WBX)
+	defined(CONFIG_SOC_SERIES_STM32WBX) || \
+	defined(CONFIG_SOC_SERIES_STM32G4X)
 	/*
-	 * L4 and WB series STM32 needs to be awaken from deep sleep mode, and
-	 * restore its calibration parameters if there are some previously
+	 * L4, WB and G4 series STM32 needs to be awaken from deep sleep mode,
+	 * and restore its calibration parameters if there are some previously
 	 * stored calibration parameters.
 	 */
 	LL_ADC_DisableDeepPowerDown(adc);
 #endif
 	/*
-	 * F3, L4, and WB ADC modules need some time to be stabilized before
+	 * F3, L4, WB and G4 ADC modules need some time to be stabilized before
 	 * performing any enable or calibration actions.
 	 */
 #if defined(CONFIG_SOC_SERIES_STM32F3X) || \
 	defined(CONFIG_SOC_SERIES_STM32L4X) || \
-	defined(CONFIG_SOC_SERIES_STM32WBX)
+	defined(CONFIG_SOC_SERIES_STM32WBX) || \
+	defined(CONFIG_SOC_SERIES_STM32G4X)
 	LL_ADC_EnableInternalRegulator(adc);
 	k_busy_wait(LL_ADC_DELAY_INTERNAL_REGUL_STAB_US);
 #endif
@@ -520,7 +526,8 @@ static int adc_stm32_init(struct device *dev)
 	LL_ADC_SetClock(adc, LL_ADC_CLOCK_SYNC_PCLK_DIV4);
 #elif defined(CONFIG_SOC_SERIES_STM32F3X) || \
 	defined(CONFIG_SOC_SERIES_STM32L4X) || \
-	defined(CONFIG_SOC_SERIES_STM32WBX)
+	defined(CONFIG_SOC_SERIES_STM32WBX) || \
+	defined(CONFIG_SOC_SERIES_STM32G4X)
 	LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(),
 			LL_ADC_CLOCK_SYNC_PCLK_DIV4);
 #endif
@@ -538,7 +545,8 @@ static int adc_stm32_init(struct device *dev)
 
 #if defined(CONFIG_SOC_SERIES_STM32F0X) || \
 	defined(CONFIG_SOC_SERIES_STM32L0X) || \
-	defined(CONFIG_SOC_SERIES_STM32WBX)
+	defined(CONFIG_SOC_SERIES_STM32WBX) || \
+	defined(CONFIG_SOC_SERIES_STM32G4X)
 	if (LL_ADC_IsActiveFlag_ADRDY(adc)) {
 		LL_ADC_ClearFlag_ADRDY(adc);
 	}
@@ -555,7 +563,8 @@ static int adc_stm32_init(struct device *dev)
 	defined(CONFIG_SOC_SERIES_STM32F3X) || \
 	defined(CONFIG_SOC_SERIES_STM32L0X) || \
 	defined(CONFIG_SOC_SERIES_STM32L4X) || \
-	defined(CONFIG_SOC_SERIES_STM32WBX)
+	defined(CONFIG_SOC_SERIES_STM32WBX) || \
+	defined(CONFIG_SOC_SERIES_STM32G4X)
 	/*
 	 * ADC modules on these series have to wait for some cycles to be
 	 * enabled.
@@ -577,11 +586,12 @@ static int adc_stm32_init(struct device *dev)
 	LL_ADC_Enable(adc);
 
 #if defined(CONFIG_SOC_SERIES_STM32L4X) || \
-	defined(CONFIG_SOC_SERIES_STM32WBX)
+	defined(CONFIG_SOC_SERIES_STM32WBX) || \
+	defined(CONFIG_SOC_SERIES_STM32G4X)
 	/*
-	 * Enabling ADC modules in L4 and WB series may fail if they are still
-	 * not stabilized, this will wait for a short time to ensure ADC modules
-	 * are properly enabled.
+	 * Enabling ADC modules in L4, WB and G4 series may fail if they are
+	 * still not stabilized, this will wait for a short time to ensure ADC
+	 * modules are properly enabled.
 	 */
 	u32_t countTimeout = 0;
 
diff --git a/soc/arm/st_stm32/stm32g4/soc.h b/soc/arm/st_stm32/stm32g4/soc.h
index f5b3e19e244..3ebea046975 100644
--- a/soc/arm/st_stm32/stm32g4/soc.h
+++ b/soc/arm/st_stm32/stm32g4/soc.h
@@ -56,6 +56,10 @@
 #include <stm32g4xx_ll_i2c.h>
 #endif /* CONFIG_I2C */
 
+#ifdef CONFIG_ADC_STM32
+#include <stm32g4xx_ll_adc.h>
+#endif
+
 #endif /* !_ASMLANGUAGE */
 
 #endif /* _STM32G4_SOC_H_ */