drivers: spi_ll_stm32: Enable SPI driver for F1 family
Enables SPI driver for STM32F1 SoCs Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
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17fcbb0507
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af0c9fc349
5 changed files with 80 additions and 22 deletions
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@ -48,6 +48,10 @@
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#include <stm32f1xx_ll_i2c.h>
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#endif
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#ifdef CONFIG_SPI_STM32
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#include <stm32f1xx_ll_spi.h>
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#endif
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#ifdef CONFIG_IWDG_STM32
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#include <stm32f1xx_ll_iwdg.h>
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#endif
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@ -11,26 +11,46 @@
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* @file Header for STM32F1 pin multiplexing helper
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*/
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#define STM32F1_PINMUX_FUNC_PA9_USART1_TX STM32_PIN_USART_TX
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#define STM32F1_PINMUX_FUNC_PA10_USART1_RX STM32_PIN_USART_RX
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#define STM32F1_PINMUX_FUNC_PA9_USART1_TX STM32_PIN_USART_TX
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#define STM32F1_PINMUX_FUNC_PA10_USART1_RX STM32_PIN_USART_RX
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#define STM32F1_PINMUX_FUNC_PA2_USART2_TX STM32_PIN_USART_TX
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#define STM32F1_PINMUX_FUNC_PA3_USART2_RX STM32_PIN_USART_RX
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#define STM32F1_PINMUX_FUNC_PA2_USART2_TX STM32_PIN_USART_TX
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#define STM32F1_PINMUX_FUNC_PA3_USART2_RX STM32_PIN_USART_RX
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#define STM32F1_PINMUX_FUNC_PD5_USART2_TX STM32_PIN_USART_TX
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#define STM32F1_PINMUX_FUNC_PD6_USART2_RX STM32_PIN_USART_RX
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#define STM32F1_PINMUX_FUNC_PA4_SPI1_MASTER_NSS STM32_PIN_SPI_MASTER_NSS
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#define STM32F1_PINMUX_FUNC_PA4_SPI1_MASTER_NSS_OE STM32_PIN_SPI_MASTER_NSS_OE
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#define STM32F1_PINMUX_FUNC_PA4_SPI1_SLAVE_NSS STM32_PIN_SPI_SLAVE_NSS
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#define STM32F1_PINMUX_FUNC_PA5_SPI1_MASTER_SCK STM32_PIN_SPI_MASTER_SCK
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#define STM32F1_PINMUX_FUNC_PA5_SPI1_SLAVE_SCK STM32_PIN_SPI_SLAVE_SCK
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#define STM32F1_PINMUX_FUNC_PA6_SPI1_MASTER_MISO STM32_PIN_SPI_MASTER_MISO
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#define STM32F1_PINMUX_FUNC_PA6_SPI1_SLAVE_MISO STM32_PIN_SPI_SLAVE_MISO
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#define STM32F1_PINMUX_FUNC_PA7_SPI1_MASTER_MOSI STM32_PIN_SPI_MASTER_MOSI
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#define STM32F1_PINMUX_FUNC_PA7_SPI1_SLAVE_MOSI STM32_PIN_SPI_SLAVE_MOSI
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#define STM32F1_PINMUX_FUNC_PB6_I2C1_SCL STM32_PIN_I2C
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#define STM32F1_PINMUX_FUNC_PB7_I2C1_SDA STM32_PIN_I2C
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#define STM32F1_PINMUX_FUNC_PB8_I2C1_SCL STM32_PIN_I2C
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#define STM32F1_PINMUX_FUNC_PB9_I2C1_SDA STM32_PIN_I2C
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#define STM32F1_PINMUX_FUNC_PD5_USART2_TX STM32_PIN_USART_TX
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#define STM32F1_PINMUX_FUNC_PD6_USART2_RX STM32_PIN_USART_RX
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#define STM32F1_PINMUX_FUNC_PB10_USART3_TX STM32_PIN_USART_TX
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#define STM32F1_PINMUX_FUNC_PB11_USART3_RX STM32_PIN_USART_RX
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#define STM32F1_PINMUX_FUNC_PB6_I2C1_SCL STM32_PIN_I2C
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#define STM32F1_PINMUX_FUNC_PB7_I2C1_SDA STM32_PIN_I2C
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#define STM32F1_PINMUX_FUNC_PB8_I2C1_SCL STM32_PIN_I2C
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#define STM32F1_PINMUX_FUNC_PB9_I2C1_SDA STM32_PIN_I2C
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#define STM32F1_PINMUX_FUNC_PB10_I2C2_SCL STM32_PIN_I2C
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#define STM32F1_PINMUX_FUNC_PB11_I2C2_SDA STM32_PIN_I2C
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#define STM32F1_PINMUX_FUNC_PB10_USART3_TX STM32_PIN_USART_TX
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#define STM32F1_PINMUX_FUNC_PB11_USART3_RX STM32_PIN_USART_RX
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#define STM32F1_PINMUX_FUNC_PA8_PWM1_CH1 STM32_PIN_PWM
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#define STM32F1_PINMUX_FUNC_PB10_I2C2_SCL STM32_PIN_I2C
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#define STM32F1_PINMUX_FUNC_PB11_I2C2_SDA STM32_PIN_I2C
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#define STM32F1_PINMUX_FUNC_PB12_SPI2_MASTER_NSS STM32_PIN_SPI_MASTER_NSS
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#define STM32F1_PINMUX_FUNC_PB12_SPI2_MASTER_NSS_OE STM32_PIN_SPI_MASTER_NSS_OE
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#define STM32F1_PINMUX_FUNC_PB12_SPI2_SLAVE_NSS STM32_PIN_SPI_SLAVE_NSS
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#define STM32F1_PINMUX_FUNC_PB13_SPI2_MASTER_SCK STM32_PIN_SPI_MASTER_SCK
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#define STM32F1_PINMUX_FUNC_PB13_SPI2_SLAVE_SCK STM32_PIN_SPI_SLAVE_SCK
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#define STM32F1_PINMUX_FUNC_PB14_SPI2_MASTER_MISO STM32_PIN_SPI_MASTER_MISO
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#define STM32F1_PINMUX_FUNC_PB14_SPI2_SLAVE_MISO STM32_PIN_SPI_SLAVE_MISO
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#define STM32F1_PINMUX_FUNC_PB15_SPI2_MASTER_MOSI STM32_PIN_SPI_MASTER_MOSI
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#define STM32F1_PINMUX_FUNC_PB15_SPI2_SLAVE_MOSI STM32_PIN_SPI_SLAVE_MOSI
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#define STM32F1_PINMUX_FUNC_PA8_PWM1_CH1 STM32_PIN_PWM
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#endif /* _STM32F1_PINMUX_H_ */
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@ -54,7 +54,6 @@ config SPI_STM32
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bool
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prompt "STM32 MCU SPI controller driver"
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depends on SPI && SOC_FAMILY_STM32
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depends on SOC_SERIES_STM32L4X || SOC_SERIES_STM32F0X || SOC_SERIES_STM32F3X || SOC_SERIES_STM32F4X
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select HAS_DTS_SPI
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select USE_STM32_LL_SPI
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default n
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@ -25,12 +25,19 @@
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#define CONFIG_DATA(cfg) \
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((struct spi_stm32_data * const)(cfg)->dev->driver_data)
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#ifdef LL_SPI_SR_UDR
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/*
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* Check for SPI_SR_FRE to determine support for TI mode frame format
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* error flag, because STM32F1 SoCs do not support it and STM32CUBE
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* for F1 family defines an unused LL_SPI_SR_FRE.
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*/
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#if defined(LL_SPI_SR_UDR)
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#define SPI_STM32_ERR_MSK (LL_SPI_SR_UDR | LL_SPI_SR_CRCERR | LL_SPI_SR_MODF | \
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LL_SPI_SR_OVR | LL_SPI_SR_FRE)
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#else
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#elif defined(SPI_SR_FRE)
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#define SPI_STM32_ERR_MSK (LL_SPI_SR_CRCERR | LL_SPI_SR_MODF | \
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LL_SPI_SR_OVR | LL_SPI_SR_FRE)
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#else
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#define SPI_STM32_ERR_MSK (LL_SPI_SR_CRCERR | LL_SPI_SR_MODF | LL_SPI_SR_OVR)
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#endif
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/* Value to shift out when no application data needs transmitting. */
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@ -313,7 +320,10 @@ static int spi_stm32_configure(struct spi_config *config)
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#if defined(CONFIG_SPI_STM32_HAS_FIFO)
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LL_SPI_SetRxFIFOThreshold(spi, LL_SPI_RX_FIFO_TH_QUARTER);
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#endif
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#ifndef CONFIG_SOC_SERIES_STM32F1X
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LL_SPI_SetStandard(spi, LL_SPI_PROTOCOL_MOTOROLA);
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#endif
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/* At this point, it's mandatory to set this on the context! */
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data->ctx.config = config;
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@ -75,10 +75,35 @@
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* registers for particular pin.
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*/
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#define STM32_PIN_USART_TX (STM32_MODE_OUTPUT | STM32_CNF_ALT_FUNC | STM32_CNF_PUSH_PULL)
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#define STM32_PIN_USART_RX (STM32_MODE_INPUT | STM32_CNF_IN_FLOAT)
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#define STM32_PIN_I2C (STM32_MODE_OUTPUT | STM32_CNF_ALT_FUNC | STM32_CNF_OPEN_DRAIN)
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#define STM32_PIN_PWM (STM32_MODE_OUTPUT | STM32_CNF_ALT_FUNC | STM32_CNF_PUSH_PULL)
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#define STM32_PIN_USART_TX (STM32_MODE_OUTPUT | STM32_CNF_ALT_FUNC | STM32_CNF_PUSH_PULL)
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#define STM32_PIN_USART_RX (STM32_MODE_INPUT | STM32_CNF_IN_FLOAT)
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#define STM32_PIN_I2C (STM32_MODE_OUTPUT | STM32_CNF_ALT_FUNC | STM32_CNF_OPEN_DRAIN)
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#define STM32_PIN_PWM (STM32_MODE_OUTPUT | STM32_CNF_ALT_FUNC | STM32_CNF_PUSH_PULL)
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#define STM32_PIN_SPI_MASTER_SCK (STM32_MODE_OUTPUT | STM32_CNF_ALT_FUNC | STM32_CNF_PUSH_PULL)
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#define STM32_PIN_SPI_SLAVE_SCK (STM32_MODE_INPUT | STM32_CNF_IN_FLOAT)
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#define STM32_PIN_SPI_MASTER_MOSI (STM32_MODE_OUTPUT | STM32_CNF_ALT_FUNC | STM32_CNF_PUSH_PULL)
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#define STM32_PIN_SPI_SLAVE_MOSI (STM32_MODE_INPUT | STM32_CNF_IN_FLOAT)
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#define STM32_PIN_SPI_MASTER_MISO (STM32_MODE_INPUT | STM32_CNF_IN_FLOAT)
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#define STM32_PIN_SPI_SLAVE_MISO (STM32_MODE_OUTPUT | STM32_CNF_ALT_FUNC | STM32_CNF_PUSH_PULL)
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/*
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* Reference manual (RM0008)
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* Section 25.3.1: Slave select (NSS) pin management
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*
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* Hardware NSS management:
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* - NSS output disabled: allows multimaster capability for devices operating
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* in master mode.
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* - NSS output enabled: used only when the device operates in master mode.
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*
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* Software NSS management:
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* - External NSS pin remains free for other application uses.
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*
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*/
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/* Hardware master NSS output disabled */
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#define STM32_PIN_SPI_MASTER_NSS (STM32_MODE_INPUT | STM32_CNF_IN_FLOAT)
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/* Hardware master NSS output enabled */
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#define STM32_PIN_SPI_MASTER_NSS_OE (STM32_MODE_OUTPUT | STM32_CNF_ALT_FUNC | STM32_CNF_PUSH_PULL)
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#define STM32_PIN_SPI_SLAVE_NSS (STM32_MODE_INPUT | STM32_CNF_IN_FLOAT)
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#endif /* _STM32_PINCTRLF1_H_ */
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