drivers: spi_ll_stm32: Enable SPI driver for F1 family

Enables SPI driver for STM32F1 SoCs

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>

arch/arm/soc/st_stm32/stm32f1/soc.h

@@ -48,6 +48,10 @@
 #include <stm32f1xx_ll_i2c.h>
 #endif
 
+#ifdef CONFIG_SPI_STM32
+#include <stm32f1xx_ll_spi.h>
+#endif
+
 #ifdef CONFIG_IWDG_STM32
 #include <stm32f1xx_ll_iwdg.h>
 #endif

drivers/pinmux/stm32/pinmux_stm32f1.h

@@ -17,6 +17,16 @@
 #define STM32F1_PINMUX_FUNC_PA2_USART2_TX	     STM32_PIN_USART_TX
 #define STM32F1_PINMUX_FUNC_PA3_USART2_RX	     STM32_PIN_USART_RX
 
+#define STM32F1_PINMUX_FUNC_PA4_SPI1_MASTER_NSS      STM32_PIN_SPI_MASTER_NSS
+#define STM32F1_PINMUX_FUNC_PA4_SPI1_MASTER_NSS_OE   STM32_PIN_SPI_MASTER_NSS_OE
+#define STM32F1_PINMUX_FUNC_PA4_SPI1_SLAVE_NSS       STM32_PIN_SPI_SLAVE_NSS
+#define STM32F1_PINMUX_FUNC_PA5_SPI1_MASTER_SCK      STM32_PIN_SPI_MASTER_SCK
+#define STM32F1_PINMUX_FUNC_PA5_SPI1_SLAVE_SCK       STM32_PIN_SPI_SLAVE_SCK
+#define STM32F1_PINMUX_FUNC_PA6_SPI1_MASTER_MISO     STM32_PIN_SPI_MASTER_MISO
+#define STM32F1_PINMUX_FUNC_PA6_SPI1_SLAVE_MISO      STM32_PIN_SPI_SLAVE_MISO
+#define STM32F1_PINMUX_FUNC_PA7_SPI1_MASTER_MOSI     STM32_PIN_SPI_MASTER_MOSI
+#define STM32F1_PINMUX_FUNC_PA7_SPI1_SLAVE_MOSI      STM32_PIN_SPI_SLAVE_MOSI
+
 #define STM32F1_PINMUX_FUNC_PD5_USART2_TX	     STM32_PIN_USART_TX
 #define STM32F1_PINMUX_FUNC_PD6_USART2_RX	     STM32_PIN_USART_RX
 
@@ -31,6 +41,16 @@
 #define STM32F1_PINMUX_FUNC_PB10_I2C2_SCL	     STM32_PIN_I2C
 #define STM32F1_PINMUX_FUNC_PB11_I2C2_SDA	     STM32_PIN_I2C
 
+#define STM32F1_PINMUX_FUNC_PB12_SPI2_MASTER_NSS     STM32_PIN_SPI_MASTER_NSS
+#define STM32F1_PINMUX_FUNC_PB12_SPI2_MASTER_NSS_OE  STM32_PIN_SPI_MASTER_NSS_OE
+#define STM32F1_PINMUX_FUNC_PB12_SPI2_SLAVE_NSS      STM32_PIN_SPI_SLAVE_NSS
+#define STM32F1_PINMUX_FUNC_PB13_SPI2_MASTER_SCK     STM32_PIN_SPI_MASTER_SCK
+#define STM32F1_PINMUX_FUNC_PB13_SPI2_SLAVE_SCK      STM32_PIN_SPI_SLAVE_SCK
+#define STM32F1_PINMUX_FUNC_PB14_SPI2_MASTER_MISO    STM32_PIN_SPI_MASTER_MISO
+#define STM32F1_PINMUX_FUNC_PB14_SPI2_SLAVE_MISO     STM32_PIN_SPI_SLAVE_MISO
+#define STM32F1_PINMUX_FUNC_PB15_SPI2_MASTER_MOSI    STM32_PIN_SPI_MASTER_MOSI
+#define STM32F1_PINMUX_FUNC_PB15_SPI2_SLAVE_MOSI     STM32_PIN_SPI_SLAVE_MOSI
+
 #define STM32F1_PINMUX_FUNC_PA8_PWM1_CH1	     STM32_PIN_PWM
 
 #endif /* _STM32F1_PINMUX_H_ */

drivers/spi/Kconfig

@@ -54,7 +54,6 @@ config SPI_STM32
 	bool
 	prompt "STM32 MCU SPI controller driver"
 	depends on SPI && SOC_FAMILY_STM32
-	depends on SOC_SERIES_STM32L4X || SOC_SERIES_STM32F0X || SOC_SERIES_STM32F3X || SOC_SERIES_STM32F4X
 	select HAS_DTS_SPI
 	select USE_STM32_LL_SPI
 	default n

drivers/spi/spi_ll_stm32.c

@@ -25,12 +25,19 @@
 #define CONFIG_DATA(cfg)					\
 ((struct spi_stm32_data * const)(cfg)->dev->driver_data)
 
-#ifdef LL_SPI_SR_UDR
+/*
+ * Check for SPI_SR_FRE to determine support for TI mode frame format
+ * error flag, because STM32F1 SoCs do not support it and  STM32CUBE
+ * for F1 family defines an unused LL_SPI_SR_FRE.
+ */
+#if defined(LL_SPI_SR_UDR)
 #define SPI_STM32_ERR_MSK (LL_SPI_SR_UDR | LL_SPI_SR_CRCERR | LL_SPI_SR_MODF | \
 			   LL_SPI_SR_OVR | LL_SPI_SR_FRE)
-#else
+#elif defined(SPI_SR_FRE)
 #define SPI_STM32_ERR_MSK (LL_SPI_SR_CRCERR | LL_SPI_SR_MODF | \
 			   LL_SPI_SR_OVR | LL_SPI_SR_FRE)
+#else
+#define SPI_STM32_ERR_MSK (LL_SPI_SR_CRCERR | LL_SPI_SR_MODF | LL_SPI_SR_OVR)
 #endif
 
 /* Value to shift out when no application data needs transmitting. */
@@ -313,7 +320,10 @@ static int spi_stm32_configure(struct spi_config *config)
 #if defined(CONFIG_SPI_STM32_HAS_FIFO)
 	LL_SPI_SetRxFIFOThreshold(spi, LL_SPI_RX_FIFO_TH_QUARTER);
 #endif
+
+#ifndef CONFIG_SOC_SERIES_STM32F1X
 	LL_SPI_SetStandard(spi, LL_SPI_PROTOCOL_MOTOROLA);
+#endif
 
 	/* At this point, it's mandatory to set this on the context! */
 	data->ctx.config = config;

include/dt-bindings/pinctrl/stm32-pinctrlf1.h

@@ -79,6 +79,31 @@
 #define STM32_PIN_USART_RX		(STM32_MODE_INPUT | STM32_CNF_IN_FLOAT)
 #define STM32_PIN_I2C			(STM32_MODE_OUTPUT | STM32_CNF_ALT_FUNC | STM32_CNF_OPEN_DRAIN)
 #define STM32_PIN_PWM			(STM32_MODE_OUTPUT | STM32_CNF_ALT_FUNC | STM32_CNF_PUSH_PULL)
+#define STM32_PIN_SPI_MASTER_SCK	(STM32_MODE_OUTPUT | STM32_CNF_ALT_FUNC | STM32_CNF_PUSH_PULL)
+#define STM32_PIN_SPI_SLAVE_SCK		(STM32_MODE_INPUT | STM32_CNF_IN_FLOAT)
+#define STM32_PIN_SPI_MASTER_MOSI	(STM32_MODE_OUTPUT | STM32_CNF_ALT_FUNC | STM32_CNF_PUSH_PULL)
+#define STM32_PIN_SPI_SLAVE_MOSI	(STM32_MODE_INPUT | STM32_CNF_IN_FLOAT)
+#define STM32_PIN_SPI_MASTER_MISO	(STM32_MODE_INPUT | STM32_CNF_IN_FLOAT)
+#define STM32_PIN_SPI_SLAVE_MISO	(STM32_MODE_OUTPUT | STM32_CNF_ALT_FUNC | STM32_CNF_PUSH_PULL)
 
+/*
+ * Reference manual (RM0008)
+ * Section 25.3.1: Slave select (NSS) pin management
+ *
+ * Hardware NSS management:
+ * - NSS output disabled: allows multimaster capability for devices operating
+ *   in master mode.
+ * - NSS output enabled: used only when the device operates in master mode.
+ *
+ * Software NSS management:
+ * - External NSS pin remains free for other application uses.
+ *
+ */
+
+/* Hardware master NSS output disabled */
+#define STM32_PIN_SPI_MASTER_NSS	(STM32_MODE_INPUT | STM32_CNF_IN_FLOAT)
+/* Hardware master NSS output enabled */
+#define STM32_PIN_SPI_MASTER_NSS_OE	(STM32_MODE_OUTPUT | STM32_CNF_ALT_FUNC | STM32_CNF_PUSH_PULL)
+#define STM32_PIN_SPI_SLAVE_NSS		(STM32_MODE_INPUT | STM32_CNF_IN_FLOAT)
 
 #endif	/* _STM32_PINCTRLF1_H_ */