From aed1f1ac5be1e0f558a6dc4a94cfa32ed9f466f5 Mon Sep 17 00:00:00 2001
From: YuLong Yao <feilongphone@gmail.com>
Date: Mon, 9 Jan 2023 20:39:05 +0800
Subject: [PATCH] drivers: gd32_adc: add support for gd32a50x series.

add support for gd32a50x series.

Signed-off-by: YuLong Yao <feilongphone@gmail.com>
---
 drivers/adc/adc_gd32.c | 22 +++++++++++++++++++++-
 1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/drivers/adc/adc_gd32.c b/drivers/adc/adc_gd32.c
index 66e5c4fa714..0a49c7af2e3 100644
--- a/drivers/adc/adc_gd32.c
+++ b/drivers/adc/adc_gd32.c
@@ -98,6 +98,20 @@ static const uint32_t table_samp_time[] = {
 	SMP_TIME(71),
 	SMP_TIME(239),
 };
+#elif defined(CONFIG_SOC_SERIES_GD32A50X)
+#define SMP_TIME(x)	ADC_SAMPLETIME_##x##POINT5
+
+static const uint16_t acq_time_tbl[8] = {3, 15, 28, 56, 84, 112, 144, 480};
+static const uint32_t table_samp_time[] = {
+	SMP_TIME(2),
+	SMP_TIME(14),
+	SMP_TIME(27),
+	SMP_TIME(55),
+	SMP_TIME(83),
+	SMP_TIME(111),
+	SMP_TIME(143),
+	SMP_TIME(479)
+};
 #else
 #define SMP_TIME(x)	ADC_SAMPLETIME_##x##POINT5
 
@@ -289,7 +303,8 @@ static int adc_gd32_start_read(const struct device *dev,
 	defined(CONFIG_SOC_SERIES_GD32L23X)
 	ADC_CTL0(cfg->reg) &= ~ADC_CTL0_DRES;
 	ADC_CTL0(cfg->reg) |= CTL0_DRES(resolution_id);
-#elif defined(CONFIG_SOC_SERIES_GD32F403)
+#elif defined(CONFIG_SOC_SERIES_GD32F403) || \
+	defined(CONFIG_SOC_SERIES_GD32A50X)
 	ADC_OVSAMPCTL(cfg->reg) &= ~ADC_OVSAMPCTL_DRES;
 	ADC_OVSAMPCTL(cfg->reg) |= OVSAMPCTL_DRES(resolution_id);
 #elif defined(CONFIG_SOC_SERIES_GD32VF103)
@@ -384,6 +399,11 @@ static int adc_gd32_init(const struct device *dev)
 	ADC_CTL1(cfg->reg) |= ADC_CTL1_ETERC;
 #endif
 
+#ifdef CONFIG_SOC_SERIES_GD32A50X
+	ADC_CTL1(cfg->reg) |= ADC_CTL1_ETSRC;
+	ADC_CTL1(cfg->reg) |= ADC_CTL1_ETERC;
+#endif
+
 	/* Enable ADC */
 	ADC_CTL1(cfg->reg) |= ADC_CTL1_ADCON;