drivers: spi: Added MEC172x full duplex qmspi driver
Add MEC172x full duplex qmspi driver version to support full duplex transfers as expected by the Zephyr spi driver model. On every spi clock we transmit one bit and receive one bit. This driver will work with Zephyr SPI NOR driver. Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
This commit is contained in:
Jay Vasanth
Maureen Helm
parent
3f1da206f8
commit
ae9de20222
9 changed files with 924 additions and 16 deletions
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@ -205,6 +205,7 @@
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&spi0 {
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status = "okay";
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compatible = "microchip,xec-qmspi-ldma";
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clock-frequency = <4000000>;
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lines = <4>;
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chip-select = <0>;
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@ -28,6 +28,7 @@ zephyr_library_sources_ifdef(CONFIG_SPI_PSOC6 spi_psoc6.c)
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zephyr_library_sources_ifdef(CONFIG_SPI_NPCX_FIU spi_npcx_fiu.c)
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zephyr_library_sources_ifdef(CONFIG_SPI_BITBANG spi_bitbang.c)
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zephyr_library_sources_ifdef(CONFIG_SPI_XEC_QMSPI_LDMA spi_xec_qmspi_ldma.c)
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zephyr_library_sources_ifdef(CONFIG_SPI_XEC_QMSPI_FULL_DUPLEX spi_xec_qmspi_full_duplex.c)
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zephyr_library_sources_ifdef(CONFIG_SPI_GD32 spi_gd32.c)
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zephyr_library_sources_ifdef(CONFIG_SPI_MCHP_QSPI spi_mchp_mss_qspi.c)
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zephyr_library_sources_ifdef(CONFIG_SPI_PL022 spi_pl022.c)
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@ -97,8 +97,6 @@ source "drivers/spi/Kconfig.npcx_fiu"
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source "drivers/spi/Kconfig.bitbang"
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source "drivers/spi/Kconfig.xec_qmspi_ldma"
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source "drivers/spi/Kconfig.gd32"
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source "drivers/spi/Kconfig.mchp_mss_qspi"
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@ -4,9 +4,23 @@
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# SPDX-License-Identifier: Apache-2.0
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config SPI_XEC_QMSPI
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bool "Microchip XEC QMSPI driver"
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bool "Microchip MEC15xx XEC QMSPI driver"
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default y
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depends on DT_HAS_MICROCHIP_XEC_QMSPI_ENABLED
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select DMA if SPI_ASYNC
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help
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Enable support for the Microchip XEC QMSPI driver.
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Enable support for Microchip MEC15xx XEC QMSPI driver.
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config SPI_XEC_QMSPI_LDMA
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bool "Microchip XEC MEC17xx QMSPI LDMA driver"
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default y
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depends on DT_HAS_MICROCHIP_XEC_QMSPI_LDMA_ENABLED
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help
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Enable support for Microchip MEC17xx QMSPI with local DMA driver.
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config SPI_XEC_QMSPI_FULL_DUPLEX
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bool "Microchip XEC MEC17xx QMSPI Full Duplex driver"
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depends on DT_HAS_MICROCHIP_XEC_QMSPI_FULL_DUPLEX_ENABLED
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help
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Enable support for Microchip MEC17xx QMSPI full duplex driver
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to work with Zephyr NOR driver
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@ -1,11 +0,0 @@
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# Microchip XEC QMSPI with LDMA
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# Copyright (c) 2021 Microchip Technology Inc.
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# SPDX-License-Identifier: Apache-2.0
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config SPI_XEC_QMSPI_LDMA
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bool "Microchip XEC QMSPI LDMA driver"
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default y
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depends on DT_HAS_MICROCHIP_XEC_QMSPI_LDMA_ENABLED
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help
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Enable support for the Microchip XEC QMSPI with local DMA driver.
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715
drivers/spi/spi_xec_qmspi_full_duplex.c
Normal file
715
drivers/spi/spi_xec_qmspi_full_duplex.c
Normal file
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@ -0,0 +1,715 @@
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/*
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* Copyright (c) 2022 Microchip Technology Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT microchip_xec_qmspi_full_duplex
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(spi_xec, CONFIG_SPI_LOG_LEVEL);
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#include <errno.h>
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#include <zephyr/device.h>
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#include <zephyr/drivers/clock_control/mchp_xec_clock_control.h>
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/drivers/interrupt_controller/intc_mchp_xec_ecia.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/drivers/pinmux.h>
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#include <zephyr/drivers/spi.h>
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#include <zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h>
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#include <zephyr/sys/__assert.h>
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#include <zephyr/sys/sys_io.h>
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#include <zephyr/sys/util.h>
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#include <soc.h>
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#include "spi_context.h"
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#include "spi_xec_qmspi_full_duplex.h"
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#if XEC_QSPI_TX_FIFO_SIZE < XEC_QSPI_RX_FIFO_SIZE
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#define XEC_QSPI_CHUNK_SIZE XEC_QSPI_TX_FIFO_SIZE
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#else
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#define XEC_QSPI_CHUNK_SIZE XEC_QSPI_RX_FIFO_SIZE
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#endif
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/* spin loops waiting for HW to clear soft reset bit */
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#define XEC_QSPI_SRST_LOOPS 16
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/* microseconds for busy wait and total wait interval */
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#define XEC_QSPI_WAIT_INTERVAL 8
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#define XEC_QSPI_WAIT_COUNT 64
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#define XEC_QSPI_WAIT_FULL_FIFO 1024
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/* 3 Tap Regs - Tap, Tap Ctrl, Tap Adjust */
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#define TAP_REGS_MAX 3
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#define CLOCK_DIV_0_VALUE 0x10000
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/*
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* Maximum number of units to generate clocks with data lines
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* tri-stated depends upon bus width. Maximum bus width is 4.
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*/
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#define XEC_QSPI_MAX_TSCLK_UNITS (MCHP_QMSPI_C_MAX_UNITS / 4)
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#define XEC_QSPI_HALF_DUPLEX 0
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#define XEC_QSPI_FULL_DUPLEX 1
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#define XEC_QSPI_DUAL 2
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#define XEC_QSPI_QUAD 4
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#define XEC_QSPI_STS_ERRORS (BIT(XEC_QSPI_STS_TXB_ERR_POS) | \
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BIT(XEC_QSPI_STS_RXB_ERR_POS) | \
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BIT(XEC_QSPI_STS_PROG_ERR_POS) | \
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BIT(XEC_QSPI_STS_LDMA_RX_ERR_POS) | \
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BIT(XEC_QSPI_STS_LDMA_TX_ERR_POS))
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#define XEC_QSPI_IEN_DONE_ERR (BIT(XEC_QSPI_IEN_XFR_DONE_POS) | \
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BIT(XEC_QSPI_IEN_TXB_ERR_POS) | \
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BIT(XEC_QSPI_IEN_RXB_ERR_POS) | \
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BIT(XEC_QSPI_IEN_PROG_ERR_POS) | \
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BIT(XEC_QSPI_IEN_LDMA_RX_ERR_POS) | \
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BIT(XEC_QSPI_IEN_LDMA_TX_ERR_POS));
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/* Device constant configuration parameters */
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struct spi_xec_qspi_config {
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struct qmspi_regs *regs;
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uint32_t cs1_freq;
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uint32_t cs_timing;
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uint16_t taps_adj;
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uint8_t girq;
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uint8_t girq_pos;
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uint8_t girq_nvic_aggr;
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uint8_t girq_nvic_direct;
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uint8_t irq_pri;
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uint8_t pcr_idx;
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uint8_t pcr_pos;
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uint8_t chip_sel;
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uint8_t width; /* 0(half) 1(single), 2(dual), 4(quad) */
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uint8_t unused[2];
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const struct pinctrl_dev_config *pcfg;
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};
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#define XEC_QMSPI_XFR_FLAG_TX BIT(0)
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#define XEC_QMSPI_XFR_FLAG_STARTED BIT(1)
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/* Device run time data */
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struct spi_xec_qspi_data {
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struct spi_context ctx;
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uint32_t qstatus;
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uint8_t np; /* number of data pins: 1, 2, or 4 */
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};
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static int xec_qspi_spin_yield(int *counter, int max_count)
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{
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*counter = *counter + 1;
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if (*counter > max_count) {
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return -ETIMEDOUT;
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}
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k_busy_wait(XEC_QSPI_WAIT_INTERVAL);
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return 0;
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}
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/*
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* reset QMSPI controller with save/restore of timing registers.
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* Some QMSPI timing register may be modified by the Boot-ROM OTP
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* values.
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*/
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static void xec_qspi_reset(struct qmspi_regs *regs)
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{
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uint32_t taps[TAP_REGS_MAX];
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uint32_t malt1;
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uint32_t cstm;
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uint32_t mode;
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uint32_t cnt = XEC_QSPI_SRST_LOOPS;
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taps[0] = regs->TM_TAPS;
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taps[1] = regs->TM_TAPS_ADJ;
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taps[2] = regs->TM_TAPS_CTRL;
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malt1 = regs->MODE_ALT1;
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cstm = regs->CSTM;
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mode = regs->MODE;
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regs->MODE = MCHP_QMSPI_M_SRST;
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while (regs->MODE & MCHP_QMSPI_M_SRST) {
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if (cnt == 0) {
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break;
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}
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cnt--;
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}
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regs->MODE = 0;
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regs->MODE = mode & ~MCHP_QMSPI_M_ACTIVATE;
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regs->CSTM = cstm;
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regs->MODE_ALT1 = malt1;
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regs->TM_TAPS = taps[0];
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regs->TM_TAPS_ADJ = taps[1];
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regs->TM_TAPS_CTRL = taps[2];
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}
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static uint32_t qspi_source_clock_freq(void)
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{
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struct pcr_regs const *pcr =
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(struct pcr_regs *)(DT_REG_ADDR_BY_IDX(DT_NODELABEL(pcr), 0));
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if (pcr->TURBO_CLK & MCHP_PCR_TURBO_CLK_96M) {
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return MEC172X_QSPI_TURBO_SRC_CLOCK_HZ;
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}
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return MEC172X_QSPI_SRC_CLOCK_HZ;
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}
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/*
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* Calculate QMSPI frequency divider register field value based upon
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* the configured QMSPI input frequency: 48 or 96 MHz.
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* The hardware divider is encoded as:
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* 0 is divide by full divider range: 256 or 65536.
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* Non-zero is divide by that value: 1 to 256 or 655356.
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*/
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static uint32_t qspi_encoded_fdiv(uint32_t freq_hz)
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{
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uint32_t fdiv = 1;
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uint32_t src_clk = qspi_source_clock_freq();
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if (freq_hz < (src_clk / 256u)) {
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fdiv = 0; /* HW fdiv = 0 is divide by 256 */
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} else if (freq_hz < src_clk) {
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/* truncated integer division may result in lower freq. */
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fdiv = src_clk / freq_hz;
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}
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return fdiv;
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}
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/* Program QMSPI frequency divider field in mode register */
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static void qspi_set_frequency(struct qmspi_regs *regs, uint32_t freq_hz)
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{
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uint32_t fdiv, mode;
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fdiv = qspi_encoded_fdiv(freq_hz);
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mode = regs->MODE & ~(XEC_QSPI_M_CLK_DIV_MASK);
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mode |= ((fdiv << XEC_QSPI_M_CLK_DIV_POS) & XEC_QSPI_M_CLK_DIV_MASK);
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regs->MODE = mode;
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}
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static uint32_t qspi_get_frequency(struct qmspi_regs *regs)
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{
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uint32_t src_clk = qspi_source_clock_freq();
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uint32_t fdiv = (regs->MODE & XEC_QSPI_M_CLK_DIV_MASK)
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>> XEC_QSPI_M_CLK_DIV_POS;
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if (fdiv == 0) {
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fdiv = CLOCK_DIV_0_VALUE;
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}
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return (src_clk / fdiv);
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}
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/*
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* SPI signalling mode: CPOL and CPHA
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* CPOL = 0 is clock idle state is low, 1 is clock idle state is high
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* CPHA = 0 Transmitter changes data on trailing of preceding clock cycle.
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* Receiver samples data on leading edge of clock cyle.
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* 1 Transmitter changes data on leading edge of current clock cycle.
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* Receiver samples data on the trailing edge of clock cycle.
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* SPI Mode nomenclature:
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* Mode CPOL CPHA
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* 0 0 0
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* 1 0 1
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* 2 1 0
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* 3 1 1
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* QMSPI has three controls, CPOL, CPHA for output and CPHA for input.
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* SPI frequency < 48MHz
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* Mode 0: CPOL=0 CHPA=0 (CHPA_MISO=0 and CHPA_MOSI=0)
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* Mode 3: CPOL=1 CHPA=1 (CHPA_MISO=1 and CHPA_MOSI=1)
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* Data sheet recommends when QMSPI set at >= 48MHz, sample and change data
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* on the same edge.
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* Mode 0: CPOL=0 CPHA=0 (CHPA_MISO=1 and CHPA_MOSI=0)
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* Mode 3: CPOL=1 CPHA=1 (CHPA_MISO=0 and CHPA_MOSI=1)
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*
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* smode_tbl and smode48_tbl has the byte values for Mode 0, 1, 2, 3
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*
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* Byte values correspond to bits 8. 9. 10 in QMSPI Mode Register
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* Bit 8 - CPOL
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* Bit 9 - CHPA MOSI
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* Bit 10 - CHPA MISO
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*/
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const uint8_t smode_tbl[4] = {
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0x00u, 0x06u, 0x01u, 0x07u
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};
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const uint8_t smode48_tbl[4] = {
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0x04u, 0x02u, 0x05u, 0x03u
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};
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static void qspi_set_signalling_mode(struct qmspi_regs *regs, uint32_t smode)
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{
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const uint8_t *ptbl;
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uint32_t m;
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ptbl = smode_tbl;
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if (qspi_get_frequency(regs) >= MHZ(48)) {
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ptbl = smode48_tbl;
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}
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m = (uint32_t)ptbl[smode & GENMASK(1, 0)];
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regs->MODE = (regs->MODE & ~(XEC_QSPI_M_CP_MSK)) |
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(m << XEC_QSPI_M_CPOL_POS);
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}
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static uint8_t npins_from_spi_config(const struct spi_config *config)
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{
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uint8_t lines = 1u;
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if (IS_ENABLED(CONFIG_SPI_EXTENDED_MODES)) {
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switch (config->operation & SPI_LINES_MASK) {
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case SPI_LINES_DUAL:
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lines = 2u;
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break;
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case SPI_LINES_QUAD:
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lines = 4u;
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break;
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default:
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lines = 1u;
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break;
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}
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}
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return lines;
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}
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/*
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* Configure QSPI.
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* NOTE: QSPI Port 0 has two chip selects available. Ports 1 & 2
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* support only CS0#.
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*/
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static int qspi_configure(const struct device *dev,
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const struct spi_config *spi_conf)
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{
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const struct spi_xec_qspi_config * const cfg = dev->config;
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struct spi_xec_qspi_data * const qdata = dev->data;
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struct qmspi_regs * const regs = cfg->regs;
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struct spi_context *ctx = &qdata->ctx;
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uint32_t smode;
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if (spi_context_configured(ctx, spi_conf)) {
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return 0;
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}
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if (spi_conf->operation & (SPI_TRANSFER_LSB | SPI_OP_MODE_SLAVE
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| SPI_MODE_LOOP)) {
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return -ENOTSUP;
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}
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if ((IS_ENABLED(CONFIG_SPI_EXTENDED_MODES) &&
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((spi_conf->operation & SPI_LINES_MASK) != SPI_LINES_SINGLE))) {
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LOG_ERR("Single(full-duplex) only");
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return -EINVAL;
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}
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if (spi_conf->operation & SPI_CS_ACTIVE_HIGH) {
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LOG_ERR("CS active high not supported");
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return -ENOTSUP;
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}
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if (SPI_WORD_SIZE_GET(spi_conf->operation) != 8) {
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LOG_ERR("Word size != 8 not supported");
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return -ENOTSUP;
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}
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smode = SPI_LINES_SINGLE;
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qdata->np = npins_from_spi_config(spi_conf);
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regs->CTRL = smode;
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/* Use the requested or next highest possible frequency */
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qspi_set_frequency(regs, spi_conf->frequency);
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smode = 0;
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if ((spi_conf->operation & SPI_MODE_CPHA) != 0U) {
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smode |= (BIT(0));
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}
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if ((spi_conf->operation & SPI_MODE_CPOL) != 0U) {
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smode |= (BIT(1));
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}
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qspi_set_signalling_mode(regs, smode);
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/* chip select */
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smode = regs->MODE & ~(XEC_QSPI_M_CS_SEL_MSK);
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if (cfg->chip_sel == 0) {
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smode |= XEC_QSPI_M_CS0_SEL;
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} else {
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smode |= XEC_QSPI_M_CS1_SEL;
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}
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regs->MODE = smode;
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/* chip select timing */
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regs->CSTM = cfg->cs_timing;
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regs->TM_TAPS_ADJ = cfg->taps_adj;
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/* CS1 alternate mode (frequency) */
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regs->MODE_ALT1 = 0;
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if (cfg->cs1_freq) {
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uint32_t fdiv = qspi_encoded_fdiv(cfg->cs1_freq);
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regs->MODE_ALT1 = (fdiv << XEC_QSPI_MALT1_CLK_DIV_POS) &
|
||||
XEC_QSPI_MALT1_CLK_DIV_MSK;
|
||||
regs->MODE_ALT1 |= BIT(XEC_QSPI_MALT1_EN_POS);
|
||||
}
|
||||
|
||||
ctx->config = spi_conf;
|
||||
|
||||
regs->MODE |= BIT(XEC_QSPI_M_ACTV_POS);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static uint32_t encode_npins(uint8_t npins)
|
||||
{
|
||||
uint32_t encoding = XEC_QSPI_C_IFC_1X;
|
||||
|
||||
if (npins == 4) {
|
||||
encoding = XEC_QSPI_C_IFC_4X;
|
||||
} else if (npins == 2) {
|
||||
encoding = XEC_QSPI_C_IFC_2X;
|
||||
} else {
|
||||
encoding = XEC_QSPI_C_IFC_1X;
|
||||
}
|
||||
|
||||
return encoding;
|
||||
}
|
||||
|
||||
/* Allocate QMSPI HW descriptor registers to process the given number of bytes
|
||||
* or until all descriptors are allocated. Returns the number of remaining
|
||||
* bytes not in allocation. Updates the word pointed to by ndescr with the
|
||||
* number of descriptors allocated. Descriptor allocation always begins with
|
||||
* descriptor 0. Descriptor QMSPI unit size, number of units, and next
|
||||
* descriptor fields are programmed other fields in descr_base are preserved.
|
||||
*/
|
||||
static size_t descr_alloc(struct qmspi_regs * const regs, size_t nbytes,
|
||||
uint32_t descr_base, uint32_t *ndescr)
|
||||
{
|
||||
size_t nb = nbytes;
|
||||
uint32_t idx = 0u;
|
||||
uint32_t descr = 0u;
|
||||
|
||||
descr_base &= ~(XEC_QSPI_C_Q_XFR_UNITS_MSK | XEC_QSPI_C_Q_NUNITS_MSK |
|
||||
XEC_QSPI_C_FN_DESCR_MSK);
|
||||
|
||||
while (nb && (idx < 16)) {
|
||||
if (nb <= XEC_QSPI_C_Q_NUNITS_MAX) {
|
||||
descr = nb;
|
||||
descr <<= XEC_QSPI_C_Q_NUNITS_POS;
|
||||
descr |= XEC_QSPI_C_Q_XFR_UNITS_1B;
|
||||
nb = 0u;
|
||||
} else {
|
||||
descr = (nb >> 4);
|
||||
nb -= (descr << 4);
|
||||
descr <<= XEC_QSPI_C_Q_NUNITS_POS;
|
||||
descr |= XEC_QSPI_C_Q_XFR_UNITS_16B;
|
||||
}
|
||||
|
||||
descr |= (XEC_QSPI_C_IFC_1X | XEC_QSPI_C_TX_EN_DATA |
|
||||
BIT(XEC_QSPI_C_RX_EN_POS));
|
||||
descr |= XEC_QSPI_C_FN_DESCR((idx + 1u));
|
||||
|
||||
regs->DESCR[idx++] = descr_base | descr;
|
||||
}
|
||||
|
||||
if (idx) {
|
||||
regs->DESCR[idx - 1u] |= BIT(XEC_QSPI_D_DESCR_LAST_POS);
|
||||
}
|
||||
|
||||
if (ndescr) {
|
||||
*ndescr = idx;
|
||||
}
|
||||
|
||||
return nb;
|
||||
}
|
||||
|
||||
/* Polling full-duplex transfer using QMSPI descriptors and FIFO's.
|
||||
* Allocate hardware descriptors for maximum total transfer size.
|
||||
* Descriptors configured for both transmit and receive.
|
||||
* If TX context has no data, transmit 0 bytes.
|
||||
* If RX context has no buffer, throw away received bytes.
|
||||
* If user set SPI_HOLD_ON_CS flag configure to not de-assert chip select
|
||||
* when the last descriptor is completed. When transfer is completed without
|
||||
* error mark context complete.
|
||||
*/
|
||||
static int xec_qspi_fd_descr(const struct device *dev,
|
||||
const struct spi_config *spi_conf,
|
||||
const struct spi_buf_set *tx_bufs,
|
||||
const struct spi_buf_set *rx_bufs)
|
||||
{
|
||||
const struct spi_xec_qspi_config *cfg = dev->config;
|
||||
struct spi_xec_qspi_data * const qdata = dev->data;
|
||||
struct qmspi_regs * const regs = cfg->regs;
|
||||
struct spi_context *ctx = &qdata->ctx;
|
||||
uint32_t descr_base, nd;
|
||||
size_t len, ntx, nrx, rem, xfr_len;
|
||||
uint8_t txb, rxb;
|
||||
bool close = true;
|
||||
|
||||
xfr_len = MAX(spi_context_total_tx_len(ctx), spi_context_total_rx_len(ctx));
|
||||
if (!xfr_len) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
regs->CTRL = 0;
|
||||
regs->EXE = BIT(XEC_QSPI_EXE_CLR_FIFOS_POS);
|
||||
regs->STS |= regs->STS;
|
||||
regs->CTRL = BIT(XEC_QSPI_C_DESCR_MODE_EN_POS);
|
||||
|
||||
descr_base = encode_npins(qdata->np);
|
||||
descr_base |= (XEC_QSPI_C_TX_EN_DATA | BIT(XEC_QSPI_C_RX_EN_POS) |
|
||||
BIT(XEC_QSPI_C_CLOSE_POS));
|
||||
|
||||
if (spi_conf->operation & SPI_HOLD_ON_CS) {
|
||||
close = false;
|
||||
}
|
||||
|
||||
len = xfr_len;
|
||||
while (len) {
|
||||
nd = 0u;
|
||||
rem = descr_alloc(regs, len, descr_base, &nd);
|
||||
|
||||
__ASSERT_NO_MSG(nd != 0);
|
||||
__ASSERT_NO_MSG(rem < len);
|
||||
|
||||
if ((rem == 0) && close) {
|
||||
regs->DESCR[nd - 1u] |= BIT(XEC_QSPI_C_CLOSE_POS);
|
||||
}
|
||||
|
||||
/* NOTE: start with TX FIFO empty causes read-only TX stall
|
||||
* status to be set.
|
||||
*/
|
||||
regs->EXE = BIT(XEC_QSPI_EXE_START_POS);
|
||||
|
||||
ntx = len - rem;
|
||||
nrx = ntx;
|
||||
while (ntx || nrx) {
|
||||
if (regs->STS & XEC_QSPI_STS_ERRORS) {
|
||||
LOG_ERR("QMSPI errors(sts): 0x%08x\n", regs->STS);
|
||||
return -EIO;
|
||||
}
|
||||
if (ntx && !(regs->STS & BIT(XEC_QSPI_STS_TXB_FULL_POS))) {
|
||||
txb = 0u;
|
||||
if (ctx->tx_buf) {
|
||||
txb = *(uint8_t *)(ctx->tx_buf);
|
||||
}
|
||||
sys_write8(txb, (mem_addr_t)®s->TX_FIFO);
|
||||
spi_context_update_tx(ctx, 1, 1);
|
||||
ntx--;
|
||||
}
|
||||
if (nrx && !(regs->STS & BIT(XEC_QSPI_STS_RXB_EMPTY_POS))) {
|
||||
rxb = sys_read8((mem_addr_t)®s->RX_FIFO);
|
||||
if (ctx->rx_buf) {
|
||||
*(uint8_t *)(ctx->rx_buf) = rxb;
|
||||
}
|
||||
spi_context_update_rx(ctx, 1, 1);
|
||||
nrx--;
|
||||
}
|
||||
}
|
||||
|
||||
len = rem;
|
||||
}
|
||||
|
||||
spi_context_complete(ctx, dev, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int xec_qspi_xfr(const struct device *dev,
|
||||
const struct spi_config *spi_conf,
|
||||
const struct spi_buf_set *tx_bufs,
|
||||
const struct spi_buf_set *rx_bufs,
|
||||
bool asynchronous)
|
||||
{
|
||||
const struct spi_xec_qspi_config *cfg = dev->config;
|
||||
struct spi_xec_qspi_data * const qdata = dev->data;
|
||||
struct qmspi_regs * const regs = cfg->regs;
|
||||
struct spi_context *ctx = &qdata->ctx;
|
||||
int ret = 0;
|
||||
|
||||
spi_context_lock(ctx, asynchronous, NULL, NULL, spi_conf);
|
||||
|
||||
ret = qspi_configure(dev, spi_conf);
|
||||
if (ret != 0) {
|
||||
spi_context_release(ctx, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
spi_context_cs_control(&qdata->ctx, true);
|
||||
spi_context_buffers_setup(ctx, tx_bufs, rx_bufs, 1);
|
||||
|
||||
ret = xec_qspi_fd_descr(dev, spi_conf, tx_bufs, rx_bufs);
|
||||
if (ret) {
|
||||
regs->EXE = BIT(XEC_QSPI_EXE_STOP_POS);
|
||||
spi_context_unlock_unconditionally(&qdata->ctx);
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (!(spi_conf->operation & SPI_HOLD_ON_CS)) {
|
||||
spi_context_cs_control(ctx, false);
|
||||
}
|
||||
|
||||
/* Attempts to take semaphore with timeout. Descriptor transfer
|
||||
* routine completes the context giving the semaphore.
|
||||
*/
|
||||
ret = spi_context_wait_for_completion(ctx);
|
||||
/* gives semaphore */
|
||||
spi_context_release(ctx, ret);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int xec_qspi_transceive(const struct device *dev,
|
||||
const struct spi_config *spi_conf,
|
||||
const struct spi_buf_set *tx_bufs,
|
||||
const struct spi_buf_set *rx_bufs)
|
||||
{
|
||||
return xec_qspi_xfr(dev, spi_conf, tx_bufs, rx_bufs, false);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SPI_ASYNC
|
||||
static int xec_qspi_transceive_async(const struct device *dev,
|
||||
const struct spi_config *spi_conf,
|
||||
const struct spi_buf_set *tx_bufs,
|
||||
const struct spi_buf_set *rx_bufs,
|
||||
struct k_poll_signal *async)
|
||||
{
|
||||
return -ENOTSUP;
|
||||
}
|
||||
#endif
|
||||
|
||||
static int xec_qspi_release(const struct device *dev,
|
||||
const struct spi_config *spi_conf)
|
||||
{
|
||||
struct spi_xec_qspi_data * const qdata = dev->data;
|
||||
const struct spi_xec_qspi_config *cfg = dev->config;
|
||||
struct qmspi_regs * const regs = cfg->regs;
|
||||
struct spi_context *ctx = &qdata->ctx;
|
||||
int ret = 0;
|
||||
int counter = 0;
|
||||
|
||||
if (regs->STS & BIT(XEC_QSPI_STS_XFR_ACTIVE_POS)) {
|
||||
/* Force CS# to de-assert on next unit boundary */
|
||||
regs->EXE = BIT(XEC_QSPI_EXE_STOP_POS);
|
||||
while (regs->STS & BIT(XEC_QSPI_STS_XFR_ACTIVE_POS)) {
|
||||
ret = xec_qspi_spin_yield(&counter,
|
||||
XEC_QSPI_WAIT_COUNT);
|
||||
if (ret != 0) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
spi_context_unlock_unconditionally(ctx);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* Called for each QMSPI controller instance
|
||||
* Initialize QMSPI controller.
|
||||
* Disable sleep control.
|
||||
* Disable and clear interrupt status.
|
||||
* Initialize SPI context.
|
||||
* QMSPI will be fully configured and enabled when the transceive API
|
||||
* is called.
|
||||
*/
|
||||
static int xec_qspi_init(const struct device *dev)
|
||||
{
|
||||
const struct spi_xec_qspi_config *cfg = dev->config;
|
||||
struct spi_xec_qspi_data * const qdata = dev->data;
|
||||
struct qmspi_regs * const regs = cfg->regs;
|
||||
int ret = 0;
|
||||
|
||||
qdata->qstatus = 0;
|
||||
qdata->np = cfg->width;
|
||||
|
||||
z_mchp_xec_pcr_periph_sleep(cfg->pcr_idx, cfg->pcr_pos, 0);
|
||||
|
||||
ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
|
||||
if (ret != 0) {
|
||||
LOG_ERR("QSPI pinctrl setup failed (%d)", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
xec_qspi_reset(regs);
|
||||
|
||||
spi_context_unlock_unconditionally(&qdata->ctx);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct spi_driver_api spi_xec_qspi_driver_api = {
|
||||
.transceive = xec_qspi_transceive,
|
||||
.release = xec_qspi_release,
|
||||
#ifdef CONFIG_SPI_ASYNC
|
||||
.transceive_async = xec_qspi_transceive_async,
|
||||
#endif
|
||||
};
|
||||
|
||||
#define XEC_QSPI_CS_TIMING_VAL(a, b, c, d) (((a) & 0xFu) \
|
||||
| (((b) & 0xFu) << 8) \
|
||||
| (((c) & 0xFu) << 16) \
|
||||
| (((d) & 0xFu) << 24))
|
||||
|
||||
#define XEC_QSPI_TAPS_ADJ_VAL(a, b) (((a) & 0xffu) | (((b) & 0xffu) << 8))
|
||||
|
||||
#define XEC_QSPI_CS_TIMING(i) XEC_QSPI_CS_TIMING_VAL( \
|
||||
DT_INST_PROP_OR(i, dcsckon, 6), \
|
||||
DT_INST_PROP_OR(i, dckcsoff, 4), \
|
||||
DT_INST_PROP_OR(i, dldh, 6), \
|
||||
DT_INST_PROP_OR(i, dcsda, 6))
|
||||
|
||||
#define XEC_QSPI_TAPS_ADJ(i) XEC_QSPI_TAPS_ADJ_VAL( \
|
||||
DT_INST_PROP_OR(i, tctradj, 0), \
|
||||
DT_INST_PROP_OR(i, tsckadj, 0))
|
||||
|
||||
#define XEC_QSPI_GIRQ(i) \
|
||||
MCHP_XEC_ECIA_GIRQ(DT_INST_PROP_BY_IDX(i, girqs, 0))
|
||||
|
||||
#define XEC_QSPI_GIRQ_POS(i) \
|
||||
MCHP_XEC_ECIA_GIRQ_POS(DT_INST_PROP_BY_IDX(i, girqs, 0))
|
||||
|
||||
#define XEC_QSPI_NVIC_AGGR(i) \
|
||||
MCHP_XEC_ECIA_NVIC_AGGR(DT_INST_PROP_BY_IDX(i, girqs, 0))
|
||||
|
||||
#define XEC_QSPI_NVIC_DIRECT(i) \
|
||||
MCHP_XEC_ECIA_NVIC_DIRECT(DT_INST_PROP_BY_IDX(i, girqs, 0))
|
||||
|
||||
/*
|
||||
* The instance number, i is not related to block ID's rather the
|
||||
* order the DT tools process all DT files in a build.
|
||||
*/
|
||||
#define XEC_QSPI_DEVICE(i) \
|
||||
\
|
||||
PINCTRL_DT_INST_DEFINE(i); \
|
||||
\
|
||||
static struct spi_xec_qspi_data xec_qspi_data_##i = { \
|
||||
SPI_CONTEXT_INIT_LOCK(xec_qspi_data_##i, ctx), \
|
||||
SPI_CONTEXT_INIT_SYNC(xec_qspi_data_##i, ctx), \
|
||||
}; \
|
||||
static const struct spi_xec_qspi_config xec_qspi_config_##i = { \
|
||||
.regs = (struct qmspi_regs *) DT_INST_REG_ADDR(i), \
|
||||
.cs1_freq = DT_INST_PROP_OR(i, cs1_freq, 0), \
|
||||
.cs_timing = XEC_QSPI_CS_TIMING(i), \
|
||||
.taps_adj = XEC_QSPI_TAPS_ADJ(i), \
|
||||
.girq = XEC_QSPI_GIRQ(i), \
|
||||
.girq_pos = XEC_QSPI_GIRQ_POS(i), \
|
||||
.girq_nvic_aggr = XEC_QSPI_NVIC_AGGR(i), \
|
||||
.girq_nvic_direct = XEC_QSPI_NVIC_DIRECT(i), \
|
||||
.irq_pri = DT_INST_IRQ(i, priority), \
|
||||
.pcr_idx = DT_INST_PROP_BY_IDX(i, pcrs, 0), \
|
||||
.pcr_pos = DT_INST_PROP_BY_IDX(i, pcrs, 1), \
|
||||
.chip_sel = DT_INST_PROP_OR(i, chip_select, 0), \
|
||||
.width = DT_INST_PROP_OR(i, lines, 1), \
|
||||
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(i), \
|
||||
}; \
|
||||
DEVICE_DT_INST_DEFINE(i, &xec_qspi_init, NULL, \
|
||||
&xec_qspi_data_##i, &xec_qspi_config_##i, \
|
||||
POST_KERNEL, CONFIG_SPI_INIT_PRIORITY, \
|
||||
&spi_xec_qspi_driver_api);
|
||||
|
||||
DT_INST_FOREACH_STATUS_OKAY(XEC_QSPI_DEVICE)
|
||||
182
drivers/spi/spi_xec_qmspi_full_duplex.h
Normal file
182
drivers/spi/spi_xec_qmspi_full_duplex.h
Normal file
|
|
@ -0,0 +1,182 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Microchip Technology Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _SPI_XEC_QMSPI_V2_H
|
||||
#define _SPI_XEC_QMSPI_V2_H
|
||||
|
||||
#define MEC152X_QSPI_SRC_CLOCK_HZ 48000000u
|
||||
#define MEC172X_QSPI_SRC_CLOCK_HZ 48000000u
|
||||
#define MEC172X_QSPI_TURBO_SRC_CLOCK_HZ 96000000u
|
||||
|
||||
#define XEC_QSPI_TX_FIFO_SIZE 8
|
||||
#define XEC_QSPI_RX_FIFO_SIZE 8
|
||||
|
||||
#define XEC_QSPI_DESCR_MAX 16
|
||||
|
||||
/* mode register */
|
||||
#define XEC_QSPI_M_ACTV_POS 0
|
||||
#define XEC_QSPI_M_SRST_POS 1
|
||||
#define XEC_QSPI_M_RX_LDMA_EN_POS 3
|
||||
#define XEC_QSPI_M_TX_LDMA_EN_POS 4
|
||||
#define XEC_QSPI_M_CPOL_POS 8
|
||||
#define XEC_QSPI_M_CPHA_MOSI_POS 9
|
||||
#define XEC_QSPI_M_CPHA_MISO_POS 10
|
||||
#define XEC_QSPI_M_CP_MSK (0x7u << XEC_QSPI_M_CPOL_POS)
|
||||
#define XEC_QSPI_M_CS_SEL_POS 12
|
||||
#define XEC_QSPI_M_CS_SEL_MSK (0x3u << XEC_QSPI_M_CS_SEL_POS)
|
||||
#define XEC_QSPI_M_CS0_SEL 0
|
||||
#define XEC_QSPI_M_CS1_SEL (1u << XEC_QSPI_M_CS_SEL_POS)
|
||||
#define XEC_QSPI_M_CLK_DIV_POS 16
|
||||
#ifdef CONFIG_SOC_SERIES_MEC172X
|
||||
#define XEC_QSPI_M_CLK_DIV_MASK 0xffff0000u
|
||||
#else
|
||||
#define XEC_QSPI_M_CLK_DIV_MASK 0xff000000u
|
||||
#endif
|
||||
|
||||
/* control register */
|
||||
#define XEC_QSPI_C_IFC_POS 0
|
||||
#define XEC_QSPI_C_IFC_MSK 0x3u
|
||||
#define XEC_QSPI_C_IFC_1X 0
|
||||
#define XEC_QSPI_C_IFC_2X 0x1u
|
||||
#define XEC_QSPI_C_IFC_4X 0x2u
|
||||
#define XEC_QSPI_C_TX_EN_POS 2
|
||||
#define XEC_QSPI_C_TX_EN_MSK (0x3u << XEC_QSPI_C_TX_EN_POS)
|
||||
#define XEC_QSPI_C_TX_EN_DATA (0x1u << XEC_QSPI_C_TX_EN_POS)
|
||||
#define XEC_QSPI_C_TX_EN_ZEROS (0x2u << XEC_QSPI_C_TX_EN_POS)
|
||||
#define XEC_QSPI_C_TX_EN_ONES (0x3u << XEC_QSPI_C_TX_EN_POS)
|
||||
#define XEC_QSPI_C_TX_DMA_EN_POS 4
|
||||
#define XEC_QSPI_C_TX_DMA_EN_MSK (0x3u << XEC_QSPI_C_TX_DMA_EN_POS)
|
||||
#define XEC_QSPI_C_TX_DMA_EN_1B (0x1u << XEC_QSPI_C_TX_DMA_EN_POS)
|
||||
#define XEC_QSPI_C_TX_DMA_EN_2B (0x2u << XEC_QSPI_C_TX_DMA_EN_POS)
|
||||
#define XEC_QSPI_C_TX_DMA_EN_4B (0x3u << XEC_QSPI_C_TX_DMA_EN_POS)
|
||||
#ifdef CONFIG_SOC_SERIES_MEC172X
|
||||
#define XEC_QSPI_C_TX_DMA_EN_LDCH0 (0x1u << XEC_QSPI_C_TX_DMA_EN_POS)
|
||||
#define XEC_QSPI_C_TX_DMA_EN_LDCH1 (0x2u << XEC_QSPI_C_TX_DMA_EN_POS)
|
||||
#define XEC_QSPI_C_TX_DMA_EN_LDCH2 (0x3u << XEC_QSPI_C_TX_DMA_EN_POS)
|
||||
#endif
|
||||
#define XEC_QSPI_C_RX_EN_POS 6
|
||||
#define XEC_QSPI_C_RX_DMA_EN_POS 7
|
||||
#define XEC_QSPI_C_RX_DMA_EN_MSK (0x3u << XEC_QSPI_C_RX_DMA_EN_POS)
|
||||
#define XEC_QSPI_C_RX_DMA_EN_1B (0x1u << XEC_QSPI_C_RX_DMA_EN_POS)
|
||||
#define XEC_QSPI_C_RX_DMA_EN_2B (0x2u << XEC_QSPI_C_RX_DMA_EN_POS)
|
||||
#define XEC_QSPI_C_RX_DMA_EN_4B (0x3u << XEC_QSPI_C_RX_DMA_EN_POS)
|
||||
#ifdef CONFIG_SOC_SERIES_MEC172X
|
||||
#define XEC_QSPI_C_RX_DMA_EN_LDCH0 (0x1u << XEC_QSPI_C_RX_DMA_EN_POS)
|
||||
#define XEC_QSPI_C_RX_DMA_EN_LDCH1 (0x2u << XEC_QSPI_C_RX_DMA_EN_POS)
|
||||
#define XEC_QSPI_C_RX_DMA_EN_LDCH2 (0x3u << XEC_QSPI_C_RX_DMA_EN_POS)
|
||||
#endif
|
||||
#define XEC_QSPI_C_CLOSE_POS 9
|
||||
#define XEC_QSPI_C_Q_XFR_UNITS_POS 10
|
||||
#define XEC_QSPI_C_Q_XFR_UNITS_MSK (0x3u << XEC_QSPI_C_Q_XFR_UNITS_POS)
|
||||
#define XEC_QSPI_C_Q_XFR_UNITS_BITS 0
|
||||
#define XEC_QSPI_C_Q_XFR_UNITS_1B (0x1u << XEC_QSPI_C_Q_XFR_UNITS_POS)
|
||||
#define XEC_QSPI_C_Q_XFR_UNITS_4B (0x2u << XEC_QSPI_C_Q_XFR_UNITS_POS)
|
||||
#define XEC_QSPI_C_Q_XFR_UNITS_16B (0x3u << XEC_QSPI_C_Q_XFR_UNITS_POS)
|
||||
#define XEC_QSPI_C_FN_DESCR_POS 12
|
||||
#define XEC_QSPI_C_FN_DESCR_MSK (0xfu << XEC_QSPI_C_FN_DESCR_POS)
|
||||
#define XEC_QSPI_C_FN_DESCR(n) \
|
||||
(((uint32_t)(n) & 0xfu) << XEC_QSPI_C_FN_DESCR_POS)
|
||||
/* control register enable descriptor mode */
|
||||
#define XEC_QSPI_C_DESCR_MODE_EN_POS 16
|
||||
/* descriptor specifies last descriptor to be processed */
|
||||
#define XEC_QSPI_D_DESCR_LAST_POS 16
|
||||
#define XEC_QSPI_C_Q_NUNITS_POS 17
|
||||
#define XEC_QSPI_C_Q_NUNITS_MAX 0x7fffu
|
||||
#define XEC_QSPI_C_Q_NUNITS_MSK (0x7fffu << XEC_QSPI_C_Q_NUNITS_POS)
|
||||
#define XEC_QSPI_C_NUNITS(n) \
|
||||
(((uint32_t)(n) & 0x7fffu) << XEC_QSPI_C_Q_NUNITS_POS)
|
||||
|
||||
/* execute register (WO). Set one bit at a time! */
|
||||
#define XEC_QSPI_EXE_START_POS 0
|
||||
#define XEC_QSPI_EXE_STOP_POS 1
|
||||
#define XEC_QSPI_EXE_CLR_FIFOS_POS 2
|
||||
|
||||
/* status register */
|
||||
#define XEC_QSPI_STS_MSK 0x0f01ff7fu
|
||||
#define XEC_QSPI_STS_MSK_RW1C 0x0000cc1fu
|
||||
#define XEC_QSPI_STS_XFR_DONE_POS 0
|
||||
#define XEC_QSPI_STS_DMA_DONE_POS 1
|
||||
#define XEC_QSPI_STS_TXB_ERR_POS 2
|
||||
#define XEC_QSPI_STS_RXB_ERR_POS 3
|
||||
#define XEC_QSPI_STS_PROG_ERR_POS 4
|
||||
#ifdef CONFIG_SOC_SERIES_MEC172X
|
||||
#define XEC_QSPI_STS_LDMA_RX_ERR_POS 5
|
||||
#define XEC_QSPI_STS_LDMA_TX_ERR_POS 6
|
||||
#endif
|
||||
#define XEC_QSPI_STS_TXB_FULL_POS 8
|
||||
#define XEC_QSPI_STS_TXB_EMPTY_POS 9
|
||||
#define XEC_QSPI_STS_TXB_REQ_POS 10
|
||||
#define XEC_QSPI_STS_TXB_STALL_POS 11
|
||||
#define XEC_QSPI_STS_RXB_FULL_POS 12
|
||||
#define XEC_QSPI_STS_RXB_EMPTY_POS 13
|
||||
#define XEC_QSPI_STS_RXB_REQ_POS 14
|
||||
#define XEC_QSPI_STS_RXB_STALL_POS 15
|
||||
#define XEC_QSPI_STS_XFR_ACTIVE_POS 16
|
||||
#define XEC_QSPI_STS_CURR_DESCR_POS 24
|
||||
#define XEC_QSPI_STS_CURR_DESCR_MSK (0xfu << XEC_QSPI_STS_CURR_DESCR_POS)
|
||||
|
||||
#define XEC_QSPI_STS_ALL_ERR (BIT(XEC_QSPI_STS_TXB_ERR_POS) | \
|
||||
BIT(XEC_QSPI_STS_RXB_ERR_POS) | \
|
||||
BIT(XEC_QSPI_STS_PROG_ERR_POS))
|
||||
|
||||
/* buffer count status (RO) */
|
||||
#define XEC_QSPI_BCNT_STS_TX_POS 0
|
||||
#define XEC_QSPI_BCNT_STS_TX_MSK 0xffffu
|
||||
#define XEC_QSPI_BCNT_STS_RX_POS 16
|
||||
#define XEC_QSPI_BCNT_STS_RX_MSK (0xffffu << XEC_QSPI_BCNT_STS_RX_POS)
|
||||
|
||||
/* interrupt enable */
|
||||
#define XEC_QSPI_IEN_XFR_DONE_POS 0
|
||||
#define XEC_QSPI_IEN_DMA_DONE_POS 1
|
||||
#define XEC_QSPI_IEN_TXB_ERR_POS 2
|
||||
#define XEC_QSPI_IEN_RXB_ERR_POS 3
|
||||
#define XEC_QSPI_IEN_PROG_ERR_POS 4
|
||||
#ifdef CONFIG_SOC_SERIES_MEC172X
|
||||
#define XEC_QSPI_IEN_LDMA_RX_ERR_POS 5
|
||||
#define XEC_QSPI_IEN_LDMA_TX_ERR_POS 6
|
||||
#endif
|
||||
#define XEC_QSPI_IEN_TXB_FULL_POS 8
|
||||
#define XEC_QSPI_IEN_TXB_EMPTY_POS 9
|
||||
#define XEC_QSPI_IEN_TXB_REQ_POS 10
|
||||
#define XEC_QSPI_IEN_RXB_FULL_POS 12
|
||||
#define XEC_QSPI_IEN_RXB_EMPTY_POS 13
|
||||
#define XEC_QSPI_IEN_RXB_REQ_POS 14
|
||||
|
||||
/* chip select timing */
|
||||
#define XEC_QSPI_CSTM_DLY_CS_TO_START_POS 0
|
||||
#define XEC_QSPI_CSTM_DLY_CS_TO_START_MSK 0xfu
|
||||
#define XEC_QSPI_CSTM_DLY_CLK_OFF_TO_CS_OFF_POS 8
|
||||
#define XEC_QSPI_CSTM_DLY_CLK_OFF_TO_CS_OFF_MSK 0xf00u
|
||||
#define XEC_QSPI_CSTM_DLY_LAST_DATA_HOLD_POS 16
|
||||
#define XEC_QSPI_CSTM_DLY_LAST_DATA_HOLD_MSK 0xf0000u
|
||||
#define XEC_QSPI_CSTM_DLY_CS_OFF_TO_CS_ON_POS 24
|
||||
#define XEC_QSPI_CSTM_DLY_CS_OFF_TO_CS_ON_MSK 0xff000000u
|
||||
|
||||
#ifdef CONFIG_SOC_SERIES_MEC172X
|
||||
#define XEC_QSPI_MALT1_EN_POS 0
|
||||
#define XEC_QSPI_MALT1_CLK_DIV_POS 16
|
||||
#define XEC_QSPI_MALT1_CLK_DIV_MSK 0xffff0000u
|
||||
|
||||
#define XEC_QSPI_LDCH_CTRL_EN_POS 0
|
||||
#define XEC_QSPI_LDCH_CTRL_RESTART_EN_POS 1
|
||||
#define XEC_QSPI_LDCH_CTRL_RESTART_ADDR_EN_POS 2
|
||||
#define XEC_QSPI_LDCH_CTRL_OVRLEN_POS 3
|
||||
#define XEC_QSPI_LDCH_CTRL_ACCSZ_POS 4
|
||||
#define XEC_QSPI_LDCH_CTRL_ACCSZ_MSK 0x30u
|
||||
#define XEC_QSPI_LDCH_CTRL_ACCSZ_1B 0u
|
||||
#define XEC_QSPI_LDCH_CTRL_ACCSZ_2B 1u
|
||||
#define XEC_QSPI_LDCH_CTRL_ACCSZ_4B 2u
|
||||
#define XEC_QSPI_LDCH_CTRL_INCR_ADDR_POS 6
|
||||
|
||||
struct qspi_ldma_chan {
|
||||
volatile uint32_t ldctrl;
|
||||
volatile uint32_t mstart;
|
||||
volatile uint32_t nbytes;
|
||||
uint32_t rsvd[1];
|
||||
};
|
||||
#endif /* CONFIG_SOC_SERIES_MEC172X */
|
||||
|
||||
#endif /* _SPI_XEC_QMSPI_V2_H */
|
||||
|
|
@ -690,7 +690,6 @@
|
|||
#size-cells = <0>;
|
||||
};
|
||||
spi0: spi@40070000 {
|
||||
compatible = "microchip,xec-qmspi-ldma";
|
||||
reg = <0x40070000 0x400>;
|
||||
interrupts = <91 2>;
|
||||
girqs = < MCHP_XEC_ECIA(18, 1, 10, 91) >;
|
||||
|
|
|
|||
9
dts/bindings/spi/microchip,xec-qmspi-full-duplex.yaml
Normal file
9
dts/bindings/spi/microchip,xec-qmspi-full-duplex.yaml
Normal file
|
|
@ -0,0 +1,9 @@
|
|||
# Copyright (c) 2018, Google LLC.
|
||||
# Copyright (c) 2022, Microchip Technology Inc.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Microchip XEC QMSPI controller with local DMA
|
||||
|
||||
compatible: "microchip,xec-qmspi-full-duplex"
|
||||
|
||||
include: [microchip-xec-qmspi-v2.yaml]
|
||||
Loading…
Add table
Add a link
Reference in a new issue