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arch/xtensa: Remember to spill windows in arch_cohere_stacks()

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When we reach this code in interrupt context, our upper GPRs contain a
cross-stack call that may still include some registers from the
interrupted thread.  Those need to go out to memory before we can do
our cache coherence dance here.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This commit is contained in:
Andy Ross 2021-03-01 11:51:28 -08:00 • committed by Anas Nashif
commit ae4f7a1a06
3 changed files with 19 additions and 6 deletions
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5
arch/xtensa/include/xtensa-asm2-s.h
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@ -326,7 +326,12 @@ _do_call_\@:
l32i a1, a1, 0
l32i a0, a1, BSA_A0_OFF
addi a1, a1, BASE_SAVE_AREA_SIZE
#ifndef CONFIG_KERNEL_COHERENCE
/* When using coherence, the registers of the interrupted
* context got spilled upstream in arch_cohere_stacks()
*/
SPILL_ALL_WINDOWS
#endif
mov a1, a6
_restore_\@: