arm: soc: nxp k6x: Add Initial support for NXP MPU

This patch adds initial MPU support to NXP K6x family.
The boot configuration prevents the following security issues:
* Prevent to read at an address that is reserved in the memory map.
* Prevent to write into the boot Flash/ROM.
* Prevent from running code located in SRAM.

This driver has been tested on FRDM-K64F.

Change-Id: I907168fff0c6028f1c665f1d3c224cbeec31be32
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>

arch/arm/soc/nxp_kinetis/Kconfig

@@ -64,6 +64,14 @@ config HAS_LPSCI
 	help
 	  Set if the low power uart (LPSCI) module is present in the SoC.
 
+config HAS_SYSMPU
+	bool "Enable MPU"
+	depends on CPU_HAS_MPU
+	select NXP_MPU
+	default n
+	help
+	  Enable MPU
+
 if HAS_OSC
 
 choice

arch/arm/soc/nxp_kinetis/k6x/Kconfig.series

@@ -12,5 +12,6 @@ config SOC_SERIES_KINETIS_K6X
 	select SOC_FAMILY_KINETIS
 	select SYS_POWER_LOW_POWER_STATE_SUPPORTED
 	select CPU_HAS_SYSTICK
+	select CPU_HAS_MPU
 	help
 	  Enable support for Kinetis K6x MCU series

arch/arm/soc/nxp_kinetis/k6x/Makefile

@@ -1,2 +1,3 @@
 obj-y += soc.o
 obj-y += wdog.o
+obj-$(CONFIG_HAS_SYSMPU) += nxp_mpu_regions.o

arch/arm/soc/nxp_kinetis/k6x/nxp_mpu_regions.c

@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2017 Linaro Limited.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <soc.h>
+#include <arch/arm/cortex_m/mpu/nxp_mpu.h>
+
+#define FLEXBUS_BASE_ADDRESS 0x08000000
+#define SRAM_L_BASE_ADDRESS 0x1FFF0000
+#define DEVICE_S_BASE_ADDRESS 0x20030000
+
+static struct nxp_mpu_region mpu_regions[] = {
+	/* Region 0 */
+	MPU_REGION_ENTRY("FLASH_0",
+			 CONFIG_FLASH_BASE_ADDRESS,
+			 0x07FFFFFF,
+			 REGION_FLASH_ATTR),
+	/* Region 1 */
+	/*
+	 * This region (Flexbus + FlexNVM) is bigger than the FLEXBUS one in
+	 * order to save 1 region allocation in the MPU.
+	 */
+	MPU_REGION_ENTRY("FLEXBUS_0",
+			 FLEXBUS_BASE_ADDRESS,
+			 0x1BFFFFFF,
+			 REGION_IO_ATTR),
+	/* Region 2 */
+	MPU_REGION_ENTRY("RAM_L_0",
+			 SRAM_L_BASE_ADDRESS,
+			 0x1FFFFFFF,
+			 REGION_RAM_ATTR),
+	/* Region 3 */
+	MPU_REGION_ENTRY("RAM_U_0",
+			 CONFIG_SRAM_BASE_ADDRESS,
+			 (CONFIG_SRAM_BASE_ADDRESS +
+				 (CONFIG_SRAM_SIZE * 1024) - 1),
+			 REGION_RAM_ATTR),
+	/* Region 4 */
+	MPU_REGION_ENTRY("DEVICE_0",
+			 DEVICE_S_BASE_ADDRESS,
+			 0xFFFFFFFF,
+			 REGION_IO_ATTR),
+};
+
+struct nxp_mpu_config mpu_config = {
+	.num_regions = ARRAY_SIZE(mpu_regions),
+	.mpu_regions = mpu_regions,
+};

arch/arm/soc/nxp_kinetis/k6x/soc.c

@@ -153,7 +153,9 @@ static int fsl_frdm_k64f_init(struct device *arg)
 	ARG_UNUSED(arg);
 
 	int oldLevel; /* old interrupt lock level */
+#if !defined(CONFIG_HAS_SYSMPU)
 	u32_t temp_reg;
+#endif /* !CONFIG_HAS_SYSMPU */
 
 	/* disable interrupts */
 	oldLevel = irq_lock();
@@ -161,6 +163,7 @@ static int fsl_frdm_k64f_init(struct device *arg)
 	/* release I/O power hold to allow normal run state */
 	PMC->REGSC |= PMC_REGSC_ACKISO_MASK;
 
+#if !defined(CONFIG_HAS_SYSMPU)
 	/*
 	 * Disable memory protection and clear slave port errors.
 	 * Note that the K64F does not implement the optional ARMv7-M memory
@@ -171,6 +174,7 @@ static int fsl_frdm_k64f_init(struct device *arg)
 	temp_reg &= ~SYSMPU_CESR_VLD_MASK;
 	temp_reg |= SYSMPU_CESR_SPERR_MASK;
 	SYSMPU->CESR = temp_reg;
+#endif /* !CONFIG_HAS_SYSMPU */
 
 	_ClearFaults();