soc: mimxrt685s/cm33: Fix lockup on clock config

Imply CONFIG_INIT_AUDIO_PLL on nxp,dmic driver selection on
mimxrt685s/cm33. Make DMIC clock config dependent on the use of the
RT685's audio PLL.

Fixes a regression described in #77851.

Signed-off-by: Vit Stanicek <vit.stanicek@nxp.com>
This commit is contained in:
Vit Stanicek 2024-09-09 09:06:08 +02:00 committed by Fabio Baltieri
commit adb83d26bf
2 changed files with 4 additions and 1 deletions

View file

@ -55,6 +55,9 @@ endif # MBEDTLS
config I2S_MCUX_FLEXCOMM config I2S_MCUX_FLEXCOMM
select INIT_AUDIO_PLL select INIT_AUDIO_PLL
config AUDIO_DMIC_MCUX
select INIT_AUDIO_PLL
if MCUX_OS_TIMER if MCUX_OS_TIMER
config SYS_CLOCK_HW_CYCLES_PER_SEC config SYS_CLOCK_HW_CYCLES_PER_SEC

View file

@ -317,7 +317,7 @@ static ALWAYS_INLINE void clock_init(void)
CLOCK_SetClkDiv(kCLOCK_DivAdcClk, DT_PROP(DT_NODELABEL(lpadc0), clk_divider)); CLOCK_SetClkDiv(kCLOCK_DivAdcClk, DT_PROP(DT_NODELABEL(lpadc0), clk_divider));
#endif #endif
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(dmic0), nxp_dmic, okay) #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(dmic0), nxp_dmic, okay) && CONFIG_INIT_AUDIO_PLL
/* Using the Audio PLL as input clock leads to better clock dividers /* Using the Audio PLL as input clock leads to better clock dividers
* for typical PCM sample rates ({8,16,24,32,48,96} kHz. * for typical PCM sample rates ({8,16,24,32,48,96} kHz.
*/ */