soc: MCXW71: Add BLE support

- Add IMU regions
- Add HCI definition
- Add config when BT is enabled

Signed-off-by: Yassine El Aissaoui <yassine.elaissaoui@nxp.com>
This commit is contained in:
Yassine El Aissaoui 2024-09-24 15:02:56 +02:00 committed by Carles Cufí
commit ad8b62413d
5 changed files with 64 additions and 5 deletions

View file

@ -1,5 +1,5 @@
/*
* Copyright 2023 NXP
* Copyright 2023-2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -10,12 +10,17 @@
#include <zephyr/dt-bindings/gpio/gpio.h>
#include <zephyr/dt-bindings/pwm/pwm.h>
#include <zephyr/dt-bindings/i2c/i2c.h>
#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
/ {
aliases {
watchdog0 = &wdog0;
};
chosen {
zephyr,bt-hci = &hci;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
@ -64,8 +69,6 @@
smu2: sram@489c0000 {
ranges = <0x0 0x489c0000 DT_SIZE_K(40)>;
#address-cells = <1>;
#size-cells = <1>;
};
peripheral: peripheral@50000000 {
@ -120,6 +123,18 @@
arm,num-irq-priority-bits = <3>;
};
&smu2 {
#address-cells = <1>;
#size-cells = <1>;
rpmsgmem: memory@8800 {
compatible = "zephyr,memory-region","mmio-sram";
reg = <0x8800 DT_SIZE_K(6)>;
zephyr,memory-region = "rpmsg_sh_mem";
zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
};
};
&pbridge2 {
#address-cells = <1>;
#size-cells = <1>;
@ -266,6 +281,12 @@
resolution = <32>;
status = "disabled";
};
hci: hci_ble {
compatible = "nxp,hci-ble";
interrupts = <48 2>;
interrupt-names = "hci_int";
};
};
&fast_peripheral0 {