diff --git a/arch/x86/core/nanocontext.c b/arch/x86/core/nanocontext.c
index 6d772d50ef6..cdffba645b9 100644
--- a/arch/x86/core/nanocontext.c
+++ b/arch/x86/core/nanocontext.c
@@ -354,7 +354,7 @@ void *_NewContext(
 	 * stack
 	 */
 
-	ccs = (tCCS *)ROUND_UP(pStackMem, CCS_ALIGN);
+	ccs = (tCCS *)ROUND_UP(pStackMem, STACK_ALIGN);
 
 	_NewContextInternal(ccs, pStackMem, stackSize, priority, options);
 
diff --git a/arch/x86/include/nanok.h b/arch/x86/include/nanok.h
index b10ca48e948..00ff5373a7f 100644
--- a/arch/x86/include/nanok.h
+++ b/arch/x86/include/nanok.h
@@ -68,31 +68,6 @@ offsets.o module.
 
 #define STACK_ALIGN_SIZE 4
 
-/*
- * Alignment requirement for the tFpRegSet structure
- *
- * If support for SSEx extensions is enabled a 16 byte boundary is required,
- * since the 'fxsave' and 'fxrstor' instructions require this.  In all other
- * cases a 4 byte bounday is sufficient.
- */
-
-#ifdef CONFIG_SSE
-#define FP_REG_SET_ALIGN 16
-#else
-#define FP_REG_SET_ALIGN 4
-#endif /* CONFIG_SSE */
-
-/*
- * Alignment requirement for the CCS structure
- *
- * The CCS must be aligned to the same boundary as that used by
- * the FP register set that appears at the end of the structure.
- * This applies even for contexts that don't initially use floating point,
- * since it is possible to enable floating point support later on.
- */
-
-#define CCS_ALIGN FP_REG_SET_ALIGN
-
 /*
  * Bitmask definitions for the tCCS->flags bit field
  *
diff --git a/include/arch/arc/arch.h b/include/arch/arc/arch.h
index 03bb3964a92..9db181c1dfc 100644
--- a/include/arch/arc/arch.h
+++ b/include/arch/arc/arch.h
@@ -60,6 +60,8 @@ extern "C" {
 #include <arch/arc/v2/arcv2_irq_unit.h>
 #endif
 
+#define STACK_ALIGN  4
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/include/arch/arm/arch.h b/include/arch/arm/arch.h
index 5e9b7b0ce51..b2e2976913f 100644
--- a/include/arch/arm/arch.h
+++ b/include/arch/arm/arch.h
@@ -64,6 +64,8 @@ extern "C" {
 #include <arch/arm/CortexM/asm_inline.h>
 #endif
 
+#define STACK_ALIGN  4
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/include/arch/x86/arch.h b/include/arch/x86/arch.h
index 39c6dd30bf2..a228b870fad 100644
--- a/include/arch/x86/arch.h
+++ b/include/arch/x86/arch.h
@@ -71,8 +71,30 @@ by the generic nanokernel interface header (nanokernel.h)
 #define _INT_STUB_ALIGN	1
 #endif
 
-typedef unsigned char __aligned(_INT_STUB_ALIGN) NANO_INT_STUB[_INT_STUB_SIZE];
+/*
+ * Floating point register set alignment.
+ *
+ * If support for SSEx extensions is enabled a 16 byte boundary is required,
+ * since the 'fxsave' and 'fxrstor' instructions require this.  In all other
+ * cases a 4 byte bounday is sufficient.
+ */
 
+#ifdef CONFIG_SSE
+#define FP_REG_SET_ALIGN  16
+#else
+#define FP_REG_SET_ALIGN  4
+#endif
+
+/*
+ * The CCS must be aligned to the same boundary as that used by the floating
+ * point register set.  This applies even for contexts that don't initially
+ * use floating point, since it is possible to enable floating point support
+ * later on.
+ */
+
+#define STACK_ALIGN  FP_REG_SET_ALIGN
+
+typedef unsigned char __aligned(_INT_STUB_ALIGN) NANO_INT_STUB[_INT_STUB_SIZE];
 
 typedef struct s_isrList {
 	void		*fnc;    /* Address of ISR/stub */
diff --git a/include/microkernel.h b/include/microkernel.h
index 85fec3994f7..63cc6eec789 100644
--- a/include/microkernel.h
+++ b/include/microkernel.h
@@ -34,6 +34,7 @@
 #define _MICROKERNEL_H
 
 #include <nanokernel.h>
+#include <arch/cpu.h>
 
 #include <cputype.h>
 #include <microkernel/k_types.h>
diff --git a/include/toolchain/common.h b/include/toolchain/common.h
index fb6c6ec4bf2..23a8105dae5 100644
--- a/include/toolchain/common.h
+++ b/include/toolchain/common.h
@@ -122,6 +122,10 @@ Macros to abstract compiler capabilities (common to all toolchains).
 
 #define _STRINGIFY(x) #x
 
+/* Indicate that an array will be used for stack space. */
+
+#define __stack __aligned(STACK_ALIGN)
+
 #ifdef CONFIG_UNALIGNED_WRITE_UNSUPPORTED
 extern void     _Unaligned32Write(unsigned int *ptr, unsigned int val);
 extern unsigned _Unaligned32Read(unsigned int *ptr);