spi: Mask tx interrupt once over with any transmission
Or then the controller will spin around requesting to get its fifo filled-in though it's unnecessary. Change-Id: I81e7c483345236dee7691c3e780b1b06d6b2d0f8 Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
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2 changed files with 7 additions and 0 deletions
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@ -94,6 +94,7 @@ DEFINE_SET_BIT_OP(sscr0_sse, INTEL_SPI_REG_SSCR0, INTEL_SPI_SSCR0_SSE_BIT)
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DEFINE_CLEAR_BIT_OP(sscr0_sse, INTEL_SPI_REG_SSCR0, INTEL_SPI_SSCR0_SSE_BIT)
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DEFINE_TEST_BIT_OP(sscr0_sse, INTEL_SPI_REG_SSCR0, INTEL_SPI_SSCR0_SSE_BIT)
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DEFINE_TEST_BIT_OP(sssr_bsy, INTEL_SPI_REG_SSSR, INTEL_SPI_SSSR_BSY_BIT)
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DEFINE_CLEAR_BIT_OP(sscr1_tie, INTEL_SPI_REG_SSRC1, INTEL_SPI_SSCR1_TIE_BIT)
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static void completed(struct device *dev, uint32_t error)
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{
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@ -165,6 +166,10 @@ static void push_data(struct device *dev)
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DBG("Pushed: %d\n", cnt);
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spi->t_len += cnt;
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if (!spi->tx_buf_len && !spi->rx_buf_len) {
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clear_bit_sscr1_tie(info->regs);
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}
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}
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static void pull_data(struct device *dev)
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@ -51,6 +51,8 @@
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((__msf && INTEL_SPI_CLK_DIV_MASK) << 8)
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/* SSCR1 settings */
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#define INTEL_SPI_SSCR1_TIE_BIT (1)
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#define INTEL_SPI_SSCR1_RIE (0x1)
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#define INTEL_SPI_SSCR1_TIE (0x1 << 1)
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#define INTEL_SPI_SSCR1_LBM (0x1 << 2)
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