spi: Mask tx interrupt once over with any transmission

Or then the controller will spin around requesting to get its fifo
filled-in though it's unnecessary.

Change-Id: I81e7c483345236dee7691c3e780b1b06d6b2d0f8
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This commit is contained in:
Tomasz Bursztyka 2015-09-11 14:23:21 +03:00 committed by Anas Nashif
commit ad35e5dacf
2 changed files with 7 additions and 0 deletions

View file

@ -94,6 +94,7 @@ DEFINE_SET_BIT_OP(sscr0_sse, INTEL_SPI_REG_SSCR0, INTEL_SPI_SSCR0_SSE_BIT)
DEFINE_CLEAR_BIT_OP(sscr0_sse, INTEL_SPI_REG_SSCR0, INTEL_SPI_SSCR0_SSE_BIT)
DEFINE_TEST_BIT_OP(sscr0_sse, INTEL_SPI_REG_SSCR0, INTEL_SPI_SSCR0_SSE_BIT)
DEFINE_TEST_BIT_OP(sssr_bsy, INTEL_SPI_REG_SSSR, INTEL_SPI_SSSR_BSY_BIT)
DEFINE_CLEAR_BIT_OP(sscr1_tie, INTEL_SPI_REG_SSRC1, INTEL_SPI_SSCR1_TIE_BIT)
static void completed(struct device *dev, uint32_t error)
{
@ -165,6 +166,10 @@ static void push_data(struct device *dev)
DBG("Pushed: %d\n", cnt);
spi->t_len += cnt;
if (!spi->tx_buf_len && !spi->rx_buf_len) {
clear_bit_sscr1_tie(info->regs);
}
}
static void pull_data(struct device *dev)

View file

@ -51,6 +51,8 @@
((__msf && INTEL_SPI_CLK_DIV_MASK) << 8)
/* SSCR1 settings */
#define INTEL_SPI_SSCR1_TIE_BIT (1)
#define INTEL_SPI_SSCR1_RIE (0x1)
#define INTEL_SPI_SSCR1_TIE (0x1 << 1)
#define INTEL_SPI_SSCR1_LBM (0x1 << 2)