soc: espressif: esp32c3: update to hal_espressif v5.1
Modify and reorganize SoC to meet updated hal. Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com> Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
This commit is contained in:
Sylvio Alves
Carles Cufí
parent
561f31bb54
commit
ad12a06e2e
13 changed files with 161 additions and 251 deletions
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@ -18,8 +18,8 @@
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#define ESP32_CLK_CPU_160M 160000000
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/* Supported XTAL Frequencies */
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#define ESP32_CLK_XTAL_32M 0U
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#define ESP32_CLK_XTAL_40M 1U
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#define ESP32_CLK_XTAL_32M 32
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#define ESP32_CLK_XTAL_40M 40
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/* Supported RTC fast clock frequencies */
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#define ESP32_RTC_FAST_CLK_FREQ_8M 8500000U
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@ -5,7 +5,7 @@ zephyr_sources(
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soc_irq.S
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soc_irq.c
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soc.c
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loader.c
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../common/loader.c
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)
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zephyr_include_directories(.)
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@ -25,52 +25,22 @@ dt_reg_addr(boot_off PATH ${dts_partition_path})
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math(EXPR esptoolpy_flashsize "${CONFIG_FLASH_SIZE} / 0x100000")
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if(CONFIG_BOOTLOADER_ESP_IDF)
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include(ExternalProject)
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## we use hello-world project, but I think any can be used.
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set(espidf_components_dir ${ESP_IDF_PATH}/components)
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set(espidf_prefix ${CMAKE_BINARY_DIR}/esp-idf)
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set(espidf_build_dir ${espidf_prefix}/build)
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set(bootloader_dir "${ZEPHYR_HAL_ESPRESSIF_MODULE_DIR}/zephyr/blobs/lib/${CONFIG_SOC_SERIES}")
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ExternalProject_Add(
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EspIdfBootloader
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PREFIX ${espidf_prefix}
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SOURCE_DIR ${espidf_components_dir}/bootloader/subproject
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BINARY_DIR ${espidf_build_dir}/bootloader
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CONFIGURE_COMMAND
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${CMAKE_COMMAND} -G${CMAKE_GENERATOR}
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-S ${espidf_components_dir}/bootloader/subproject
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-B ${espidf_build_dir}/bootloader -DSDKCONFIG=${espidf_build_dir}/sdkconfig
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-DIDF_PATH=${ESP_IDF_PATH} -DIDF_TARGET=${CONFIG_SOC_SERIES}
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-DPYTHON_DEPS_CHECKED=1
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-DCMAKE_C_COMPILER=${CMAKE_C_COMPILER}
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-DCMAKE_CXX_COMPILER=${CMAKE_CXX_COMPILER}
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-DCMAKE_ASM_COMPILER=${CMAKE_ASM_COMPILER}
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-DCMAKE_SYSTEM_NAME=${CMAKE_SYSTEM_NAME}
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-DPYTHON=${PYTHON_EXECUTABLE}
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BUILD_COMMAND
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${CMAKE_COMMAND} --build .
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INSTALL_COMMAND "" # This particular build system has no install command
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)
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if(EXISTS "${bootloader_dir}/bootloader-${CONFIG_SOC_SERIES}.bin")
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file(COPY "${bootloader_dir}/bootloader-${CONFIG_SOC_SERIES}.bin" DESTINATION ${CMAKE_BINARY_DIR})
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file(RENAME "${CMAKE_BINARY_DIR}/bootloader-${CONFIG_SOC_SERIES}.bin" "${CMAKE_BINARY_DIR}/bootloader.bin")
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endif()
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ExternalProject_Add(
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EspPartitionTable
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SOURCE_DIR ${espidf_components_dir}/partition_table
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BINARY_DIR ${espidf_build_dir}
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CONFIGURE_COMMAND ""
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BUILD_COMMAND
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${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/partition_table/gen_esp32part.py -q
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--offset 0x8000 --flash-size ${esptoolpy_flashsize}MB ${ESP_IDF_PATH}/components/partition_table/partitions_singleapp.csv ${espidf_build_dir}/partitions_singleapp.bin
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INSTALL_COMMAND ""
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)
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if(EXISTS "${bootloader_dir}/partition-table-${CONFIG_SOC_SERIES}.bin")
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file(COPY "${bootloader_dir}/partition-table-${CONFIG_SOC_SERIES}.bin" DESTINATION ${CMAKE_BINARY_DIR})
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file(RENAME "${CMAKE_BINARY_DIR}/partition-table-${CONFIG_SOC_SERIES}.bin" "${CMAKE_BINARY_DIR}/partition-table.bin")
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endif()
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set_property(TARGET bintools PROPERTY disassembly_flag_inline_source)
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board_finalize_runner_args(esp32 "--esp-flash-bootloader=${CMAKE_BINARY_DIR}/bootloader.bin")
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add_dependencies(app EspIdfBootloader EspPartitionTable)
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board_finalize_runner_args(esp32 "--esp-flash-bootloader=${espidf_build_dir}/bootloader/bootloader.bin")
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board_finalize_runner_args(esp32 "--esp-flash-partition_table=${espidf_build_dir}/partitions_singleapp.bin")
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board_finalize_runner_args(esp32 "--esp-flash-partition_table=${CMAKE_BINARY_DIR}/partition-table.bin")
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board_finalize_runner_args(esp32 "--esp-partition-table-address=0x8000")
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@ -80,7 +50,7 @@ if(CONFIG_MCUBOOT OR CONFIG_BOOTLOADER_ESP_IDF)
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if(CONFIG_BUILD_OUTPUT_BIN)
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set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
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COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/esptool_py/esptool/esptool.py
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COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/tools/esptool_py/esptool.py
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ARGS --chip esp32c3 elf2image --flash_mode dio --flash_freq 40m --flash_size ${esptoolpy_flashsize}MB
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-o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin
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${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf)
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@ -22,56 +22,6 @@ config IDF_TARGET_ESP32C3
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bool "ESP32C3 as target board"
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default y
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config ESP_SYSTEM_RTC_EXT_XTAL
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bool
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config ESP_SYSTEM_RTC_EXT_OSC
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bool
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choice ESP32C3_RTC_CLK_SRC
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prompt "RTC clock source"
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default ESP32C3_RTC_CLK_SRC_INT_RC
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help
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Choose which clock is used as RTC clock source.
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config ESP32C3_RTC_CLK_SRC_INT_RC
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bool "Internal 150kHz RC oscillator"
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config ESP32C3_RTC_CLK_SRC_EXT_CRYS
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bool "External 32kHz crystal"
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select ESP_SYSTEM_RTC_EXT_XTAL
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config ESP32C3_RTC_CLK_SRC_EXT_OSC
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bool "External 32kHz oscillator at 32K_XP pin"
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select ESP_SYSTEM_RTC_EXT_OSC
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config ESP32C3_RTC_CLK_SRC_INT_8MD256
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bool "Internal 8MHz oscillator, divided by 256 (~32kHz)"
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endchoice # ESP32C3_RTC_CLK_SRC
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config ESP32C3_RTC_CLK_CAL_CYCLES
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int "Number of cycles for RTC_SLOW_CLK calibration"
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default 3000 if ESP32C3_RTC_CLK_SRC_EXT_CRYS || ESP32C3_RTC_CLK_SRC_EXT_OSC || ESP32C3_RTC_CLK_SRC_INT_8MD256
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default 1024 if ESP32C3_RTC_CLK_SRC_INT_RC
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range 0 27000 if ESP32C3_RTC_CLK_SRC_EXT_CRYS || ESP32C3_RTC_CLK_SRC_EXT_OSC || ESP32C3_RTC_CLK_SRC_INT_8MD256
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range 0 32766 if ESP32C3_RTC_CLK_SRC_INT_RC
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help
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When the startup code initializes RTC_SLOW_CLK, it can perform
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calibration by comparing the RTC_SLOW_CLK frequency with main XTAL
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frequency. This option sets the number of RTC_SLOW_CLK cycles measured
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by the calibration routine. Higher numbers increase calibration
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precision, which may be important for applications which spend a lot of
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time in deep sleep. Lower numbers reduce startup time.
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When this option is set to 0, clock calibration will not be performed at
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startup, and approximate clock frequencies will be assumed:
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- 150000 Hz if internal RC oscillator is used as clock source. For this use value 1024.
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- 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more.
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In case more value will help improve the definition of the launch of the crystal.
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If the crystal could not start, it will be switched to internal RC.
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config ESP32_PHY_MAX_WIFI_TX_POWER
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int "Max WiFi TX power (dBm)"
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range 10 20
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@ -6,9 +6,6 @@ if SOC_SERIES_ESP32C3
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config NUM_IRQS
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default 62
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config ESPTOOLPY_FLASHFREQ_80M
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default y
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config FLASH_SIZE
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default $(dt_node_reg_size_int,/soc/flash-controller@60002000/flash@0,0)
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48
soc/espressif/esp32c3/Kconfig.mac
Normal file
48
soc/espressif/esp32c3/Kconfig.mac
Normal file
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@ -0,0 +1,48 @@
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# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
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# SPDX-License-Identifier: Apache-2.0
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if SOC_SERIES_ESP32C3
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choice ESP32C3_UNIVERSAL_MAC_ADDRESSES
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bool "Number of universally administered (by IEEE) MAC address"
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default ESP32C3_UNIVERSAL_MAC_ADDRESSES_FOUR
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help
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Configure the number of universally administered (by IEEE) MAC addresses.
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During initialization, MAC addresses for each network interface are generated or derived from a
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single base MAC address.
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If the number of universal MAC addresses is four, all four interfaces (WiFi station, WiFi softap,
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Bluetooth and Ethernet) receive a universally administered MAC address. These are generated
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sequentially by adding 0, 1, 2 and 3 (respectively) to the final octet of the base MAC address.
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If the number of universal MAC addresses is two, only two interfaces (WiFi station and Bluetooth)
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receive a universally administered MAC address. These are generated sequentially by adding 0
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and 1 (respectively) to the base MAC address. The remaining two interfaces (WiFi softap and Ethernet)
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receive local MAC addresses. These are derived from the universal WiFi station and Bluetooth MAC
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addresses, respectively.
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When using the default (Espressif-assigned) base MAC address, either setting can be used. When using
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a custom universal MAC address range, the correct setting will depend on the allocation of MAC
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addresses in this range (either 2 or 4 per device.)
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Note that ESP32-C3 has no integrated Ethernet MAC. Although it's possible to use the esp_read_mac()
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API to return a MAC for Ethernet, this can only be used with an external MAC peripheral.
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config ESP32C3_UNIVERSAL_MAC_ADDRESSES_TWO
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bool "Two"
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select ESP_MAC_UNIVERSAL_MAC_ADDRESSES_TWO
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select ESP_MAC_ADDR_UNIVERSE_WIFI_STA
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select ESP_MAC_ADDR_UNIVERSE_BT
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config ESP32C3_UNIVERSAL_MAC_ADDRESSES_FOUR
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bool "Four"
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select ESP_MAC_UNIVERSAL_MAC_ADDRESSES_FOUR
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select ESP_MAC_ADDR_UNIVERSE_WIFI_STA
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select ESP_MAC_ADDR_UNIVERSE_WIFI_AP
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select ESP_MAC_ADDR_UNIVERSE_BT
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select ESP_MAC_ADDR_UNIVERSE_ETH
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endchoice # ESP32C3_UNIVERSAL_MAC_ADDRESSES
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config ESP32C3_UNIVERSAL_MAC_ADDRESSES
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int
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default 2 if ESP32C3_UNIVERSAL_MAC_ADDRESSES_TWO
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default 4 if ESP32C3_UNIVERSAL_MAC_ADDRESSES_FOUR
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endif # SOC_SERIES_ESP32C3
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50
soc/espressif/esp32c3/Kconfig.rtc
Normal file
50
soc/espressif/esp32c3/Kconfig.rtc
Normal file
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@ -0,0 +1,50 @@
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# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
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# SPDX-License-Identifier: Apache-2.0
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if SOC_SERIES_ESP32C3
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choice RTC_CLK_SRC
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prompt "RTC clock source"
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default RTC_CLK_SRC_INT_RC
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help
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Choose which clock is used as RTC clock source.
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config RTC_CLK_SRC_INT_RC
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bool "Internal 136kHz RC oscillator"
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config RTC_CLK_SRC_EXT_CRYS
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bool "External 32kHz crystal"
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select ESP_SYSTEM_RTC_EXT_XTAL
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config RTC_CLK_SRC_EXT_OSC
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bool "External 32kHz oscillator at 32K_XP pin"
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select ESP_SYSTEM_RTC_EXT_OSC
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config RTC_CLK_SRC_INT_8MD256
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bool "Internal 17.5MHz oscillator, divided by 256"
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endchoice # ESP32C3_RTC_CLK_SRC
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config RTC_CLK_CAL_CYCLES
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int "Number of cycles for RTC_SLOW_CLK calibration"
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default 3000 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC || RTC_CLK_SRC_INT_8MD256
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default 1024 if RTC_CLK_SRC_INT_RC
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range 0 27000 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC || RTC_CLK_SRC_INT_8MD256
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range 0 32766 if RTC_CLK_SRC_INT_RC
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help
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When the startup code initializes RTC_SLOW_CLK, it can perform
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calibration by comparing the RTC_SLOW_CLK frequency with main XTAL
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frequency. This option sets the number of RTC_SLOW_CLK cycles measured
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by the calibration routine. Higher numbers increase calibration
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precision, which may be important for applications which spend a lot of
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time in deep sleep. Lower numbers reduce startup time.
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When this option is set to 0, clock calibration will not be performed at
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startup, and approximate clock frequencies will be assumed:
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- 150000 Hz if internal RC oscillator is used as clock source. For this use value 1024.
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- 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more.
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In case more value will help improve the definition of the launch of the crystal.
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If the crystal could not start, it will be switched to internal RC.
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endif # SOC_SERIES_ESP32C3
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@ -247,6 +247,8 @@ SECTIONS
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*libdrivers__console.a:uart_console.*(.literal.console_out .text.console_out)
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*libzephyr.a:log_output.*(.literal .text .literal.* .text.*)
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*libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*)
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*libzephyr.a:cache_hal.*(.literal .text .literal.* .text.*)
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*libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*)
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*libzephyr.a:loader.*(.literal .text .literal.* .text.*)
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*libsoc.a:rtc_*.*(.literal .text .literal.* .text.*)
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*libsoc.a:cpu_util.*(.literal .text .literal.* .text.*)
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@ -335,6 +337,8 @@ SECTIONS
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*libzephyr.a:log_core.*(.rodata .rodata.*)
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*libzephyr.a:log_backend_uart.*(.rodata .rodata.*)
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*libzephyr.a:log_output.*(.rodata .rodata.*)
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*libzephyr.a:cache_hal.*(.rodata .rodata.*)
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*libzephyr.a:mmu_hal.*(.rodata .rodata.*)
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*libzephyr.a:loader.*(.rodata .rodata.*)
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*libdrivers__flash.a:flash_esp32.*(.rodata .rodata.*)
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*libdrivers__serial.a:uart_esp32.*(.rodata .rodata.*)
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@ -404,6 +408,7 @@ SECTIONS
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.flash.text : ALIGN(IROM_SEG_ALIGN)
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{
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_stext = .;
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_instruction_reserved_start = ABSOLUTE(.);
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_text_start = ABSOLUTE(.);
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#if !defined(CONFIG_ESP32_WIFI_IRAM_OPT)
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@ -431,6 +436,7 @@ SECTIONS
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. += 16;
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_text_end = ABSOLUTE(.);
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_instruction_reserved_end = ABSOLUTE(.);
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_etext = .;
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/**
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@ -1,93 +0,0 @@
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/*
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* Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <esp32c3/rom/cache.h>
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#include "soc/cache_memory.h"
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#include "soc/extmem_reg.h"
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#include <bootloader_flash_priv.h>
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#include <zephyr/kernel.h>
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#include <soc.h>
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#include <zephyr/storage/flash_map.h>
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#include <esp_log.h>
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#include <stdlib.h>
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#ifdef CONFIG_BOOTLOADER_MCUBOOT
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#define BOOT_LOG_INF(_fmt, ...) \
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ets_printf("[" CONFIG_SOC_SERIES "] [INF] " _fmt "\n\r", ##__VA_ARGS__)
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#define HDR_ATTR __attribute__((section(".entry_addr"))) __attribute__((used))
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extern uint32_t _image_irom_start, _image_irom_size, _image_irom_vaddr;
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extern uint32_t _image_drom_start, _image_drom_size, _image_drom_vaddr;
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void __start(void);
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static HDR_ATTR void (*_entry_point)(void) = &__start;
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static int map_rom_segments(void)
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{
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int rc = 0;
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size_t _partition_offset = FIXED_PARTITION_OFFSET(slot0_partition);
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uint32_t _app_irom_start = _partition_offset + (uint32_t)&_image_irom_start;
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uint32_t _app_irom_size = (uint32_t)&_image_irom_size;
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uint32_t _app_irom_vaddr = (uint32_t)&_image_irom_vaddr;
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uint32_t _app_drom_start = _partition_offset + (uint32_t)&_image_drom_start;
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uint32_t _app_drom_size = (uint32_t)&_image_drom_size;
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uint32_t _app_drom_vaddr = (uint32_t)&_image_drom_vaddr;
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uint32_t autoload = esp_rom_Cache_Suspend_ICache();
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esp_rom_Cache_Invalidate_ICache_All();
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/* Clear the MMU entries that are already set up,
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* so the new app only has the mappings it creates.
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*/
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for (size_t i = 0; i < FLASH_MMU_TABLE_SIZE; i++) {
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FLASH_MMU_TABLE[i] = MMU_TABLE_INVALID_VAL;
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}
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uint32_t drom_page_count = bootloader_cache_pages_to_map(_app_drom_size, _app_drom_vaddr);
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rc |= esp_rom_Cache_Dbus_MMU_Set(MMU_ACCESS_FLASH, _app_drom_vaddr & 0xffff0000,
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_app_drom_start & 0xffff0000, 64, drom_page_count, 0);
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uint32_t irom_page_count = bootloader_cache_pages_to_map(_app_irom_size, _app_irom_vaddr);
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rc |= esp_rom_Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, _app_irom_vaddr & 0xffff0000,
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_app_irom_start & 0xffff0000, 64, irom_page_count, 0);
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REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_IBUS);
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REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_DBUS);
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esp_rom_Cache_Resume_ICache(autoload);
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||||
/* Show map segments continue using same log format as during MCUboot phase */
|
||||
BOOT_LOG_INF("DROM segment: paddr=%08Xh, vaddr=%08Xh, size=%05Xh (%6d) map",
|
||||
_app_drom_start, _app_drom_vaddr, _app_drom_size, _app_drom_size);
|
||||
BOOT_LOG_INF("IROM segment: paddr=%08Xh, vaddr=%08Xh, size=%05Xh (%6d) map\r\n",
|
||||
_app_irom_start, _app_irom_vaddr, _app_irom_size, _app_irom_size);
|
||||
esp_rom_uart_tx_wait_idle(0);
|
||||
|
||||
return rc;
|
||||
}
|
||||
#endif /* CONFIG_BOOTLOADER_MCUBOOT */
|
||||
|
||||
void __start(void)
|
||||
{
|
||||
#ifdef CONFIG_BOOTLOADER_MCUBOOT
|
||||
int err = map_rom_segments();
|
||||
|
||||
if (err != 0) {
|
||||
ets_printf("Failed to setup XIP, aborting\n");
|
||||
abort();
|
||||
}
|
||||
#endif
|
||||
__esp_platform_start();
|
||||
}
|
||||
|
|
@ -35,9 +35,9 @@
|
|||
/* Global symbols required for espressif hal build */
|
||||
MEMORY
|
||||
{
|
||||
iram_seg (RX) : org = 0x403CA000, len = 0x6000
|
||||
iram_loader_seg (RX) : org = 0x403D0000, len = 0x4000
|
||||
dram_seg (RW) : org = 0x3FCD8000, len = 0x8000
|
||||
iram_seg (RX) : org = 0x403CA000, len = 0x9000
|
||||
iram_loader_seg (RX) : org = 0x403D3000, len = 0x4000
|
||||
dram_seg (RW) : org = 0x3FCD8000, len = 0x9000
|
||||
|
||||
#ifdef CONFIG_GEN_ISR_TABLES
|
||||
IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000
|
||||
|
|
@ -134,7 +134,8 @@ SECTIONS
|
|||
*(.sdata2)
|
||||
*(.sdata2.*)
|
||||
*(.gnu.linkonce.s2.*)
|
||||
|
||||
*libzephyr.a:mmu_hal.*(.rodata .rodata.*)
|
||||
*libzephyr.a:rtc_clk.*(.rodata .rodata.*)
|
||||
KEEP(*(.jcr))
|
||||
*(.dram1 .dram1.*)
|
||||
. = ALIGN(4);
|
||||
|
|
@ -227,6 +228,10 @@ SECTIONS
|
|||
*libzephyr.a:esp_efuse_api_key_esp32xx.*(.literal .text .literal.* .text.*)
|
||||
*esp_mcuboot.*(.literal .text .literal.* .text.*)
|
||||
*esp_loader.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:rtc_clk.*(.literal .literal.* .text .text.*)
|
||||
*libzephyr.a:rtc_clk_init.*(.literal .literal.* .text .text.*)
|
||||
*libzephyr.a:rtc_time.*(.literal .literal.* .text .text.*)
|
||||
*(.fini.literal)
|
||||
*(.fini)
|
||||
*(.gnu.version)
|
||||
|
|
|
|||
|
|
@ -10,6 +10,6 @@
|
|||
void z_sys_poweroff(void)
|
||||
{
|
||||
/* Forces RTC domain to be always on */
|
||||
esp_sleep_pd_config(ESP_PD_DOMAIN_RTC_PERIPH, ESP_PD_OPTION_ON);
|
||||
esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL, ESP_PD_OPTION_ON);
|
||||
esp_deep_sleep_start();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -7,17 +7,21 @@
|
|||
/* Include esp-idf headers first to avoid redefining BIT() macro */
|
||||
#include <soc/rtc_cntl_reg.h>
|
||||
#include <soc/timer_group_reg.h>
|
||||
#include <soc/ext_mem_defs.h>
|
||||
#include <soc/gpio_reg.h>
|
||||
#include <soc/syscon_reg.h>
|
||||
#include <soc/system_reg.h>
|
||||
#include <soc/cache_memory.h>
|
||||
#include "hal/soc_ll.h"
|
||||
#include "hal/wdt_hal.h"
|
||||
#include "esp_cpu.h"
|
||||
#include "hal/soc_hal.h"
|
||||
#include "hal/cpu_hal.h"
|
||||
#include "esp_timer.h"
|
||||
#include "esp_spi_flash.h"
|
||||
#include "esp_private/system_internal.h"
|
||||
#include "esp_clk_internal.h"
|
||||
#include <soc/interrupt_reg.h>
|
||||
#include <esp_private/spi_flash_os.h>
|
||||
#include "esp_private/esp_mmu_map_private.h"
|
||||
|
||||
#include <zephyr/drivers/interrupt_controller/intc_esp32c3.h>
|
||||
|
||||
#include <zephyr/kernel_structs.h>
|
||||
|
|
@ -82,9 +86,9 @@ void __attribute__((section(".iram1"))) __esp_platform_start(void)
|
|||
|
||||
extern int _rodata_reserved_start;
|
||||
uint32_t rodata_reserved_start_align =
|
||||
(uint32_t)&_rodata_reserved_start & ~(MMU_PAGE_SIZE - 1);
|
||||
(uint32_t)&_rodata_reserved_start & ~(CONFIG_MMU_PAGE_SIZE - 1);
|
||||
uint32_t cache_mmu_irom_size =
|
||||
((rodata_reserved_start_align - SOC_DROM_LOW) / MMU_PAGE_SIZE) *
|
||||
((rodata_reserved_start_align - SOC_DROM_LOW) / CONFIG_MMU_PAGE_SIZE) *
|
||||
sizeof(uint32_t);
|
||||
|
||||
esp_rom_cache_set_idrom_mmu_size(cache_mmu_irom_size,
|
||||
|
|
@ -96,6 +100,22 @@ void __attribute__((section(".iram1"))) __esp_platform_start(void)
|
|||
REG_CLR_BIT(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_SDIOSLAVE_EN);
|
||||
SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_EN);
|
||||
|
||||
#ifdef CONFIG_SOC_FLASH_ESP32
|
||||
esp_mspi_pin_init();
|
||||
|
||||
/**
|
||||
* This function initialise the Flash chip to the user-defined settings.
|
||||
*
|
||||
* In bootloader, we only init Flash (and MSPI) to a preliminary state, for being flexible to
|
||||
* different chips.
|
||||
* In this stage, we re-configure the Flash (and MSPI) to required configuration
|
||||
*/
|
||||
spi_flash_init_chip_state();
|
||||
|
||||
esp_mmu_map_init();
|
||||
|
||||
#endif /*CONFIG_SOC_FLASH_ESP32*/
|
||||
|
||||
/* Configures the CPU clock, RTC slow and fast clocks, and performs
|
||||
* RTC slow clock calibration.
|
||||
*/
|
||||
|
|
@ -128,52 +148,6 @@ int IRAM_ATTR arch_printk_char_out(int c)
|
|||
return 0;
|
||||
}
|
||||
|
||||
void IRAM_ATTR esp_restart_noos(void)
|
||||
{
|
||||
/* Disable interrupts */
|
||||
csr_read_clear(mstatus, MSTATUS_MIE);
|
||||
|
||||
/* Flush any data left in UART FIFOs */
|
||||
esp_rom_uart_tx_wait_idle(0);
|
||||
esp_rom_uart_tx_wait_idle(1);
|
||||
|
||||
/* 2nd stage bootloader reconfigures SPI flash signals. */
|
||||
/* Reset them to the defaults expected by ROM */
|
||||
WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30);
|
||||
WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30);
|
||||
WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30);
|
||||
WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30);
|
||||
WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30);
|
||||
WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30);
|
||||
|
||||
/* Reset wifi/bluetooth/ethernet/sdio (bb/mac) */
|
||||
SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG,
|
||||
SYSTEM_BB_RST | SYSTEM_FE_RST | SYSTEM_MAC_RST | SYSTEM_BT_RST |
|
||||
SYSTEM_BTMAC_RST | SYSTEM_SDIO_RST | SYSTEM_EMAC_RST |
|
||||
SYSTEM_MACPWR_RST | SYSTEM_RW_BTMAC_RST | SYSTEM_RW_BTLP_RST |
|
||||
BLE_REG_REST_BIT | BLE_PWR_REG_REST_BIT | BLE_BB_REG_REST_BIT);
|
||||
|
||||
REG_WRITE(SYSTEM_CORE_RST_EN_REG, 0);
|
||||
|
||||
/* Reset uart0 core first, then reset apb side. */
|
||||
SET_PERI_REG_MASK(UART_CLK_CONF_REG(0), UART_RST_CORE_M);
|
||||
|
||||
/* Reset timer/spi/uart */
|
||||
SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG,
|
||||
SYSTEM_TIMERS_RST | SYSTEM_SPI01_RST | SYSTEM_UART_RST);
|
||||
REG_WRITE(SYSTEM_PERIP_RST_EN0_REG, 0);
|
||||
/* Reset dma */
|
||||
SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST);
|
||||
REG_WRITE(SYSTEM_PERIP_RST_EN1_REG, 0);
|
||||
|
||||
/* Reset core */
|
||||
soc_ll_reset_core(0);
|
||||
|
||||
while (true) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void sys_arch_reboot(int type)
|
||||
{
|
||||
esp_restart_noos();
|
||||
|
|
|
|||
|
|
@ -13,13 +13,18 @@
|
|||
#include <rom/spi_flash.h>
|
||||
#include <zephyr/types.h>
|
||||
#include <stdbool.h>
|
||||
#include "esp32c3/clk.h"
|
||||
#include <esp_private/esp_clk.h>
|
||||
#endif
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
void __esp_platform_start(void);
|
||||
|
||||
static inline uint32_t esp_core_id(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
extern void esp_rom_intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num);
|
||||
extern void esp_rom_uart_attach(void);
|
||||
extern void esp_rom_uart_tx_wait_idle(uint8_t uart_no);
|
||||
|
|
@ -40,7 +45,6 @@ extern int esp_rom_Cache_Dbus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t
|
|||
extern int esp_rom_Cache_Ibus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr,
|
||||
uint32_t psize, uint32_t num, uint32_t fixed);
|
||||
extern void esp_rom_Cache_Resume_ICache(uint32_t autoload);
|
||||
extern spiflash_legacy_data_t esp_rom_spiflash_legacy_data;
|
||||
extern int esp_rom_gpio_matrix_in(uint32_t gpio, uint32_t signal_index,
|
||||
bool inverted);
|
||||
extern int esp_rom_gpio_matrix_out(uint32_t gpio, uint32_t signal_index,
|
||||
|
|
|
|||
|
|
@ -6,11 +6,10 @@
|
|||
|
||||
#include <soc/rtc_cntl_reg.h>
|
||||
#include <soc/timer_group_reg.h>
|
||||
#include <soc/ext_mem_defs.h>
|
||||
#include <soc/gpio_reg.h>
|
||||
#include <soc/syscon_reg.h>
|
||||
#include <soc/system_reg.h>
|
||||
#include <soc/cache_memory.h>
|
||||
#include "hal/soc_ll.h"
|
||||
#include <riscv/interrupt.h>
|
||||
#include <soc/interrupt_reg.h>
|
||||
#include <soc/periph_defs.h>
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue