soc: espressif: esp32c3: update to hal_espressif v5.1

Modify and reorganize SoC to meet updated hal.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>

include/zephyr/dt-bindings/clock/esp32c3_clock.h

@@ -18,8 +18,8 @@
 #define ESP32_CLK_CPU_160M             160000000
 
 /* Supported XTAL Frequencies */
-#define ESP32_CLK_XTAL_32M             0U
+#define ESP32_CLK_XTAL_32M             32
-#define ESP32_CLK_XTAL_40M             1U
+#define ESP32_CLK_XTAL_40M             40
 
 /* Supported RTC fast clock frequencies */
 #define ESP32_RTC_FAST_CLK_FREQ_8M     8500000U

soc/espressif/esp32c3/CMakeLists.txt

@@ -5,7 +5,7 @@ zephyr_sources(
   soc_irq.S
   soc_irq.c
   soc.c
-  loader.c
+  ../common/loader.c
   )
 
 zephyr_include_directories(.)
@@ -25,52 +25,22 @@ dt_reg_addr(boot_off PATH ${dts_partition_path})
 math(EXPR esptoolpy_flashsize "${CONFIG_FLASH_SIZE} / 0x100000")
 
 if(CONFIG_BOOTLOADER_ESP_IDF)
-  include(ExternalProject)
 
-  ## we use hello-world project, but I think any can be used.
+  set(bootloader_dir "${ZEPHYR_HAL_ESPRESSIF_MODULE_DIR}/zephyr/blobs/lib/${CONFIG_SOC_SERIES}")
-  set(espidf_components_dir   ${ESP_IDF_PATH}/components)
-  set(espidf_prefix    ${CMAKE_BINARY_DIR}/esp-idf)
-  set(espidf_build_dir ${espidf_prefix}/build)
 
-  ExternalProject_Add(
+  if(EXISTS "${bootloader_dir}/bootloader-${CONFIG_SOC_SERIES}.bin")
-    EspIdfBootloader
+    file(COPY "${bootloader_dir}/bootloader-${CONFIG_SOC_SERIES}.bin" DESTINATION ${CMAKE_BINARY_DIR})
-    PREFIX ${espidf_prefix}
+    file(RENAME "${CMAKE_BINARY_DIR}/bootloader-${CONFIG_SOC_SERIES}.bin" "${CMAKE_BINARY_DIR}/bootloader.bin")
-    SOURCE_DIR ${espidf_components_dir}/bootloader/subproject
+  endif()
-    BINARY_DIR ${espidf_build_dir}/bootloader
-    CONFIGURE_COMMAND
-    ${CMAKE_COMMAND} -G${CMAKE_GENERATOR}
-    -S ${espidf_components_dir}/bootloader/subproject
-    -B ${espidf_build_dir}/bootloader -DSDKCONFIG=${espidf_build_dir}/sdkconfig
-    -DIDF_PATH=${ESP_IDF_PATH} -DIDF_TARGET=${CONFIG_SOC_SERIES}
-    -DPYTHON_DEPS_CHECKED=1
-    -DCMAKE_C_COMPILER=${CMAKE_C_COMPILER}
-    -DCMAKE_CXX_COMPILER=${CMAKE_CXX_COMPILER}
-    -DCMAKE_ASM_COMPILER=${CMAKE_ASM_COMPILER}
-    -DCMAKE_SYSTEM_NAME=${CMAKE_SYSTEM_NAME}
-    -DPYTHON=${PYTHON_EXECUTABLE}
-    BUILD_COMMAND
-    ${CMAKE_COMMAND} --build .
-    INSTALL_COMMAND ""      # This particular build system has no install command
-    )
 
-  ExternalProject_Add(
+  if(EXISTS "${bootloader_dir}/partition-table-${CONFIG_SOC_SERIES}.bin")
-    EspPartitionTable
+    file(COPY "${bootloader_dir}/partition-table-${CONFIG_SOC_SERIES}.bin" DESTINATION ${CMAKE_BINARY_DIR})
-    SOURCE_DIR ${espidf_components_dir}/partition_table
+    file(RENAME "${CMAKE_BINARY_DIR}/partition-table-${CONFIG_SOC_SERIES}.bin" "${CMAKE_BINARY_DIR}/partition-table.bin")
-    BINARY_DIR ${espidf_build_dir}
+  endif()
-    CONFIGURE_COMMAND ""
-    BUILD_COMMAND
-    ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/partition_table/gen_esp32part.py -q
-    --offset 0x8000 --flash-size ${esptoolpy_flashsize}MB ${ESP_IDF_PATH}/components/partition_table/partitions_singleapp.csv ${espidf_build_dir}/partitions_singleapp.bin
-    INSTALL_COMMAND ""
-    )
 
-  set_property(TARGET bintools PROPERTY disassembly_flag_inline_source)
+  board_finalize_runner_args(esp32 "--esp-flash-bootloader=${CMAKE_BINARY_DIR}/bootloader.bin")
 
-  add_dependencies(app EspIdfBootloader EspPartitionTable)
+  board_finalize_runner_args(esp32 "--esp-flash-partition_table=${CMAKE_BINARY_DIR}/partition-table.bin")
-
-  board_finalize_runner_args(esp32 "--esp-flash-bootloader=${espidf_build_dir}/bootloader/bootloader.bin")
-
-  board_finalize_runner_args(esp32 "--esp-flash-partition_table=${espidf_build_dir}/partitions_singleapp.bin")
 
   board_finalize_runner_args(esp32 "--esp-partition-table-address=0x8000")
 
@@ -80,7 +50,7 @@ if(CONFIG_MCUBOOT OR CONFIG_BOOTLOADER_ESP_IDF)
 
   if(CONFIG_BUILD_OUTPUT_BIN)
     set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
-      COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/esptool_py/esptool/esptool.py
+      COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/tools/esptool_py/esptool.py
       ARGS --chip esp32c3 elf2image --flash_mode dio --flash_freq 40m --flash_size ${esptoolpy_flashsize}MB
       -o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin
       ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf)

soc/espressif/esp32c3/Kconfig

@@ -22,56 +22,6 @@ config IDF_TARGET_ESP32C3
 	bool "ESP32C3 as target board"
 	default y
 
-config ESP_SYSTEM_RTC_EXT_XTAL
-	bool
-
-config ESP_SYSTEM_RTC_EXT_OSC
-	bool
-
-choice ESP32C3_RTC_CLK_SRC
-	prompt "RTC clock source"
-	default ESP32C3_RTC_CLK_SRC_INT_RC
-	help
-	  Choose which clock is used as RTC clock source.
-
-config ESP32C3_RTC_CLK_SRC_INT_RC
-	bool "Internal 150kHz RC oscillator"
-
-config ESP32C3_RTC_CLK_SRC_EXT_CRYS
-	bool "External 32kHz crystal"
-	select ESP_SYSTEM_RTC_EXT_XTAL
-
-config ESP32C3_RTC_CLK_SRC_EXT_OSC
-	bool "External 32kHz oscillator at 32K_XP pin"
-	select ESP_SYSTEM_RTC_EXT_OSC
-
-config ESP32C3_RTC_CLK_SRC_INT_8MD256
-	bool "Internal 8MHz oscillator, divided by 256 (~32kHz)"
-
-endchoice # ESP32C3_RTC_CLK_SRC
-
-config ESP32C3_RTC_CLK_CAL_CYCLES
-	int "Number of cycles for RTC_SLOW_CLK calibration"
-	default 3000 if ESP32C3_RTC_CLK_SRC_EXT_CRYS || ESP32C3_RTC_CLK_SRC_EXT_OSC || ESP32C3_RTC_CLK_SRC_INT_8MD256
-	default 1024 if ESP32C3_RTC_CLK_SRC_INT_RC
-	range 0 27000 if ESP32C3_RTC_CLK_SRC_EXT_CRYS || ESP32C3_RTC_CLK_SRC_EXT_OSC || ESP32C3_RTC_CLK_SRC_INT_8MD256
-	range 0 32766 if ESP32C3_RTC_CLK_SRC_INT_RC
-	help
-	  When the startup code initializes RTC_SLOW_CLK, it can perform
-	  calibration by comparing the RTC_SLOW_CLK frequency with main XTAL
-	  frequency. This option sets the number of RTC_SLOW_CLK cycles measured
-	  by the calibration routine. Higher numbers increase calibration
-	  precision, which may be important for applications which spend a lot of
-	  time in deep sleep. Lower numbers reduce startup time.
-
-	  When this option is set to 0, clock calibration will not be performed at
-	  startup, and approximate clock frequencies will be assumed:
-
-	  - 150000 Hz if internal RC oscillator is used as clock source. For this use value 1024.
-	  - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more.
-	    In case more value will help improve the definition of the launch of the crystal.
-	    If the crystal could not start, it will be switched to internal RC.
-
 config ESP32_PHY_MAX_WIFI_TX_POWER
 	int "Max WiFi TX power (dBm)"
 	range 10 20

soc/espressif/esp32c3/Kconfig.defconfig

@@ -6,9 +6,6 @@ if SOC_SERIES_ESP32C3
 config NUM_IRQS
 	default 62
 
-config ESPTOOLPY_FLASHFREQ_80M
-	default y
-
 config FLASH_SIZE
 	default $(dt_node_reg_size_int,/soc/flash-controller@60002000/flash@0,0)
 

soc/espressif/esp32c3/Kconfig.mac

@@ -0,0 +1,48 @@
+# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_ESP32C3
+
+choice ESP32C3_UNIVERSAL_MAC_ADDRESSES
+	bool "Number of universally administered (by IEEE) MAC address"
+	default ESP32C3_UNIVERSAL_MAC_ADDRESSES_FOUR
+	help
+	  Configure the number of universally administered (by IEEE) MAC addresses.
+	  During initialization, MAC addresses for each network interface are generated or derived from a
+	  single base MAC address.
+	  If the number of universal MAC addresses is four, all four interfaces (WiFi station, WiFi softap,
+	  Bluetooth and Ethernet) receive a universally administered MAC address. These are generated
+	  sequentially by adding 0, 1, 2 and 3 (respectively) to the final octet of the base MAC address.
+	  If the number of universal MAC addresses is two, only two interfaces (WiFi station and Bluetooth)
+	  receive a universally administered MAC address. These are generated sequentially by adding 0
+	  and 1 (respectively) to the base MAC address. The remaining two interfaces (WiFi softap and Ethernet)
+	  receive local MAC addresses. These are derived from the universal WiFi station and Bluetooth MAC
+	  addresses, respectively.
+	  When using the default (Espressif-assigned) base MAC address, either setting can be used. When using
+	  a custom universal MAC address range, the correct setting will depend on the allocation of MAC
+	  addresses in this range (either 2 or 4 per device.)
+	  Note that ESP32-C3 has no integrated Ethernet MAC. Although it's possible to use the esp_read_mac()
+	  API to return a MAC for Ethernet, this can only be used with an external MAC peripheral.
+
+config ESP32C3_UNIVERSAL_MAC_ADDRESSES_TWO
+	bool "Two"
+	select ESP_MAC_UNIVERSAL_MAC_ADDRESSES_TWO
+	select ESP_MAC_ADDR_UNIVERSE_WIFI_STA
+	select ESP_MAC_ADDR_UNIVERSE_BT
+
+config ESP32C3_UNIVERSAL_MAC_ADDRESSES_FOUR
+	bool "Four"
+	select ESP_MAC_UNIVERSAL_MAC_ADDRESSES_FOUR
+	select ESP_MAC_ADDR_UNIVERSE_WIFI_STA
+	select ESP_MAC_ADDR_UNIVERSE_WIFI_AP
+	select ESP_MAC_ADDR_UNIVERSE_BT
+	select ESP_MAC_ADDR_UNIVERSE_ETH
+
+endchoice # ESP32C3_UNIVERSAL_MAC_ADDRESSES
+
+config ESP32C3_UNIVERSAL_MAC_ADDRESSES
+	int
+	default 2 if ESP32C3_UNIVERSAL_MAC_ADDRESSES_TWO
+	default 4 if ESP32C3_UNIVERSAL_MAC_ADDRESSES_FOUR
+
+endif # SOC_SERIES_ESP32C3

soc/espressif/esp32c3/Kconfig.rtc

@@ -0,0 +1,50 @@
+# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_ESP32C3
+
+choice RTC_CLK_SRC
+	prompt "RTC clock source"
+	default RTC_CLK_SRC_INT_RC
+	help
+	  Choose which clock is used as RTC clock source.
+
+config RTC_CLK_SRC_INT_RC
+	bool "Internal 136kHz RC oscillator"
+
+config RTC_CLK_SRC_EXT_CRYS
+	bool "External 32kHz crystal"
+	select ESP_SYSTEM_RTC_EXT_XTAL
+
+config RTC_CLK_SRC_EXT_OSC
+	bool "External 32kHz oscillator at 32K_XP pin"
+	select ESP_SYSTEM_RTC_EXT_OSC
+
+config RTC_CLK_SRC_INT_8MD256
+	bool "Internal 17.5MHz oscillator, divided by 256"
+
+endchoice # ESP32C3_RTC_CLK_SRC
+
+config RTC_CLK_CAL_CYCLES
+	int "Number of cycles for RTC_SLOW_CLK calibration"
+	default 3000 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC || RTC_CLK_SRC_INT_8MD256
+	default 1024 if RTC_CLK_SRC_INT_RC
+	range 0 27000 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC || RTC_CLK_SRC_INT_8MD256
+	range 0 32766 if RTC_CLK_SRC_INT_RC
+	help
+	  When the startup code initializes RTC_SLOW_CLK, it can perform
+	  calibration by comparing the RTC_SLOW_CLK frequency with main XTAL
+	  frequency. This option sets the number of RTC_SLOW_CLK cycles measured
+	  by the calibration routine. Higher numbers increase calibration
+	  precision, which may be important for applications which spend a lot of
+	  time in deep sleep. Lower numbers reduce startup time.
+
+	  When this option is set to 0, clock calibration will not be performed at
+	  startup, and approximate clock frequencies will be assumed:
+
+	  - 150000 Hz if internal RC oscillator is used as clock source. For this use value 1024.
+	  - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more.
+	    In case more value will help improve the definition of the launch of the crystal.
+	    If the crystal could not start, it will be switched to internal RC.
+
+endif # SOC_SERIES_ESP32C3

soc/espressif/esp32c3/default.ld

@@ -247,6 +247,8 @@ SECTIONS
     *libdrivers__console.a:uart_console.*(.literal.console_out .text.console_out)
     *libzephyr.a:log_output.*(.literal .text .literal.* .text.*)
     *libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*)
+    *libzephyr.a:cache_hal.*(.literal .text .literal.* .text.*)
+    *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*)
     *libzephyr.a:loader.*(.literal .text .literal.* .text.*)
     *libsoc.a:rtc_*.*(.literal .text .literal.* .text.*)
     *libsoc.a:cpu_util.*(.literal .text .literal.* .text.*)
@@ -335,6 +337,8 @@ SECTIONS
     *libzephyr.a:log_core.*(.rodata .rodata.*)
     *libzephyr.a:log_backend_uart.*(.rodata .rodata.*)
     *libzephyr.a:log_output.*(.rodata .rodata.*)
+    *libzephyr.a:cache_hal.*(.rodata .rodata.*)
+    *libzephyr.a:mmu_hal.*(.rodata .rodata.*)
     *libzephyr.a:loader.*(.rodata .rodata.*)
     *libdrivers__flash.a:flash_esp32.*(.rodata  .rodata.*)
     *libdrivers__serial.a:uart_esp32.*(.rodata .rodata.*)
@@ -404,6 +408,7 @@ SECTIONS
   .flash.text : ALIGN(IROM_SEG_ALIGN)
   {
     _stext = .;
+    _instruction_reserved_start = ABSOLUTE(.);
     _text_start = ABSOLUTE(.);
 
 #if !defined(CONFIG_ESP32_WIFI_IRAM_OPT)
@@ -431,6 +436,7 @@ SECTIONS
     . += 16;
 
     _text_end = ABSOLUTE(.);
+    _instruction_reserved_end = ABSOLUTE(.);
     _etext = .;
 
     /**

soc/espressif/esp32c3/loader.c

@@ -1,93 +0,0 @@
-/*
- * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <esp32c3/rom/cache.h>
-#include "soc/cache_memory.h"
-#include "soc/extmem_reg.h"
-#include <bootloader_flash_priv.h>
-
-#include <zephyr/kernel.h>
-#include <soc.h>
-#include <zephyr/storage/flash_map.h>
-#include <esp_log.h>
-#include <stdlib.h>
-
-#ifdef CONFIG_BOOTLOADER_MCUBOOT
-
-#define BOOT_LOG_INF(_fmt, ...) \
-	ets_printf("[" CONFIG_SOC_SERIES "] [INF] " _fmt "\n\r", ##__VA_ARGS__)
-
-#define HDR_ATTR __attribute__((section(".entry_addr"))) __attribute__((used))
-
-extern uint32_t _image_irom_start, _image_irom_size, _image_irom_vaddr;
-extern uint32_t _image_drom_start, _image_drom_size, _image_drom_vaddr;
-
-void __start(void);
-
-static HDR_ATTR void (*_entry_point)(void) = &__start;
-
-static int map_rom_segments(void)
-{
-	int rc = 0;
-
-	size_t _partition_offset = FIXED_PARTITION_OFFSET(slot0_partition);
-	uint32_t _app_irom_start = _partition_offset + (uint32_t)&_image_irom_start;
-	uint32_t _app_irom_size = (uint32_t)&_image_irom_size;
-	uint32_t _app_irom_vaddr = (uint32_t)&_image_irom_vaddr;
-
-	uint32_t _app_drom_start = _partition_offset + (uint32_t)&_image_drom_start;
-	uint32_t _app_drom_size = (uint32_t)&_image_drom_size;
-	uint32_t _app_drom_vaddr = (uint32_t)&_image_drom_vaddr;
-
-	uint32_t autoload = esp_rom_Cache_Suspend_ICache();
-
-	esp_rom_Cache_Invalidate_ICache_All();
-
-	/* Clear the MMU entries that are already set up,
-	 * so the new app only has the mappings it creates.
-	 */
-	for (size_t i = 0; i < FLASH_MMU_TABLE_SIZE; i++) {
-		FLASH_MMU_TABLE[i] = MMU_TABLE_INVALID_VAL;
-	}
-
-	uint32_t drom_page_count = bootloader_cache_pages_to_map(_app_drom_size, _app_drom_vaddr);
-
-	rc |= esp_rom_Cache_Dbus_MMU_Set(MMU_ACCESS_FLASH, _app_drom_vaddr & 0xffff0000,
-				_app_drom_start & 0xffff0000, 64, drom_page_count, 0);
-
-	uint32_t irom_page_count = bootloader_cache_pages_to_map(_app_irom_size, _app_irom_vaddr);
-
-	rc |= esp_rom_Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, _app_irom_vaddr & 0xffff0000,
-				_app_irom_start & 0xffff0000, 64, irom_page_count, 0);
-
-	REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_IBUS);
-	REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_DBUS);
-
-	esp_rom_Cache_Resume_ICache(autoload);
-
-	/* Show map segments continue using same log format as during MCUboot phase */
-	BOOT_LOG_INF("DROM segment: paddr=%08Xh, vaddr=%08Xh, size=%05Xh (%6d) map",
-		_app_drom_start, _app_drom_vaddr, _app_drom_size, _app_drom_size);
-	BOOT_LOG_INF("IROM segment: paddr=%08Xh, vaddr=%08Xh, size=%05Xh (%6d) map\r\n",
-		_app_irom_start, _app_irom_vaddr, _app_irom_size, _app_irom_size);
-	esp_rom_uart_tx_wait_idle(0);
-
-	return rc;
-}
-#endif /* CONFIG_BOOTLOADER_MCUBOOT */
-
-void __start(void)
-{
-#ifdef CONFIG_BOOTLOADER_MCUBOOT
-	int err = map_rom_segments();
-
-	if (err != 0) {
-		ets_printf("Failed to setup XIP, aborting\n");
-		abort();
-	}
-#endif
-	__esp_platform_start();
-}

soc/espressif/esp32c3/mcuboot.ld

@@ -35,9 +35,9 @@
 /* Global symbols required for espressif hal build */
 MEMORY
 {
-  iram_seg        (RX) : org = 0x403CA000, len = 0x6000
+  iram_seg        (RX) : org = 0x403CA000, len = 0x9000
-  iram_loader_seg (RX) : org = 0x403D0000, len = 0x4000
+  iram_loader_seg (RX) : org = 0x403D3000, len = 0x4000
-  dram_seg        (RW) : org = 0x3FCD8000, len = 0x8000
+  dram_seg        (RW) : org = 0x3FCD8000, len = 0x9000
 
 #ifdef CONFIG_GEN_ISR_TABLES
   IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000
@@ -134,7 +134,8 @@ SECTIONS
     *(.sdata2)
     *(.sdata2.*)
     *(.gnu.linkonce.s2.*)
-
+    *libzephyr.a:mmu_hal.*(.rodata .rodata.*)
+    *libzephyr.a:rtc_clk.*(.rodata .rodata.*)
     KEEP(*(.jcr))
     *(.dram1 .dram1.*)
     . = ALIGN(4);
@@ -227,6 +228,10 @@ SECTIONS
     *libzephyr.a:esp_efuse_api_key_esp32xx.*(.literal .text .literal.* .text.*)
     *esp_mcuboot.*(.literal .text .literal.* .text.*)
     *esp_loader.*(.literal .text .literal.* .text.*)
+    *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*)
+    *libzephyr.a:rtc_clk.*(.literal .literal.* .text .text.*)
+    *libzephyr.a:rtc_clk_init.*(.literal .literal.* .text .text.*)
+    *libzephyr.a:rtc_time.*(.literal .literal.* .text .text.*)
     *(.fini.literal)
     *(.fini)
     *(.gnu.version)

soc/espressif/esp32c3/poweroff.c

@@ -10,6 +10,6 @@
 void z_sys_poweroff(void)
 {
 	/* Forces RTC domain to be always on */
-	esp_sleep_pd_config(ESP_PD_DOMAIN_RTC_PERIPH, ESP_PD_OPTION_ON);
+	esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL, ESP_PD_OPTION_ON);
 	esp_deep_sleep_start();
 }

soc/espressif/esp32c3/soc.c

@@ -7,17 +7,21 @@
 /* Include esp-idf headers first to avoid redefining BIT() macro */
 #include <soc/rtc_cntl_reg.h>
 #include <soc/timer_group_reg.h>
+#include <soc/ext_mem_defs.h>
 #include <soc/gpio_reg.h>
 #include <soc/syscon_reg.h>
 #include <soc/system_reg.h>
-#include <soc/cache_memory.h>
-#include "hal/soc_ll.h"
 #include "hal/wdt_hal.h"
 #include "esp_cpu.h"
+#include "hal/soc_hal.h"
+#include "hal/cpu_hal.h"
 #include "esp_timer.h"
-#include "esp_spi_flash.h"
+#include "esp_private/system_internal.h"
 #include "esp_clk_internal.h"
 #include <soc/interrupt_reg.h>
+#include <esp_private/spi_flash_os.h>
+#include "esp_private/esp_mmu_map_private.h"
+
 #include <zephyr/drivers/interrupt_controller/intc_esp32c3.h>
 
 #include <zephyr/kernel_structs.h>
@@ -82,9 +86,9 @@ void __attribute__((section(".iram1"))) __esp_platform_start(void)
 
 	extern int _rodata_reserved_start;
 	uint32_t rodata_reserved_start_align =
-		(uint32_t)&_rodata_reserved_start & ~(MMU_PAGE_SIZE - 1);
+		(uint32_t)&_rodata_reserved_start & ~(CONFIG_MMU_PAGE_SIZE - 1);
 	uint32_t cache_mmu_irom_size =
-		((rodata_reserved_start_align - SOC_DROM_LOW) / MMU_PAGE_SIZE) *
+		((rodata_reserved_start_align - SOC_DROM_LOW) / CONFIG_MMU_PAGE_SIZE) *
 			sizeof(uint32_t);
 
 	esp_rom_cache_set_idrom_mmu_size(cache_mmu_irom_size,
@@ -96,6 +100,22 @@ void __attribute__((section(".iram1"))) __esp_platform_start(void)
 	REG_CLR_BIT(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_SDIOSLAVE_EN);
 	SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_EN);
 
+#ifdef CONFIG_SOC_FLASH_ESP32
+	esp_mspi_pin_init();
+
+    /**
+     * This function initialise the Flash chip to the user-defined settings.
+     *
+     * In bootloader, we only init Flash (and MSPI) to a preliminary state, for being flexible to
+     * different chips.
+     * In this stage, we re-configure the Flash (and MSPI) to required configuration
+     */
+	spi_flash_init_chip_state();
+
+	esp_mmu_map_init();
+
+#endif /*CONFIG_SOC_FLASH_ESP32*/
+
 	/* Configures the CPU clock, RTC slow and fast clocks, and performs
 	 * RTC slow clock calibration.
 	 */
@@ -128,52 +148,6 @@ int IRAM_ATTR arch_printk_char_out(int c)
 	return 0;
 }
 
-void IRAM_ATTR esp_restart_noos(void)
-{
-	/* Disable interrupts */
-	csr_read_clear(mstatus, MSTATUS_MIE);
-
-	/* Flush any data left in UART FIFOs */
-	esp_rom_uart_tx_wait_idle(0);
-	esp_rom_uart_tx_wait_idle(1);
-
-	/* 2nd stage bootloader reconfigures SPI flash signals. */
-	/* Reset them to the defaults expected by ROM */
-	WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30);
-	WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30);
-	WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30);
-	WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30);
-	WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30);
-	WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30);
-
-	/* Reset wifi/bluetooth/ethernet/sdio (bb/mac) */
-	SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG,
-			SYSTEM_BB_RST | SYSTEM_FE_RST | SYSTEM_MAC_RST | SYSTEM_BT_RST |
-			SYSTEM_BTMAC_RST | SYSTEM_SDIO_RST | SYSTEM_EMAC_RST |
-			SYSTEM_MACPWR_RST | SYSTEM_RW_BTMAC_RST | SYSTEM_RW_BTLP_RST |
-			BLE_REG_REST_BIT | BLE_PWR_REG_REST_BIT | BLE_BB_REG_REST_BIT);
-
-	REG_WRITE(SYSTEM_CORE_RST_EN_REG, 0);
-
-	/* Reset uart0 core first, then reset apb side. */
-	SET_PERI_REG_MASK(UART_CLK_CONF_REG(0), UART_RST_CORE_M);
-
-	/* Reset timer/spi/uart */
-	SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG,
-				SYSTEM_TIMERS_RST | SYSTEM_SPI01_RST | SYSTEM_UART_RST);
-	REG_WRITE(SYSTEM_PERIP_RST_EN0_REG, 0);
-	/* Reset dma */
-	SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST);
-	REG_WRITE(SYSTEM_PERIP_RST_EN1_REG, 0);
-
-	/* Reset core */
-	soc_ll_reset_core(0);
-
-	while (true) {
-		;
-	}
-}
-
 void sys_arch_reboot(int type)
 {
 	esp_restart_noos();

soc/espressif/esp32c3/soc.h

@@ -13,13 +13,18 @@
 #include <rom/spi_flash.h>
 #include <zephyr/types.h>
 #include <stdbool.h>
-#include "esp32c3/clk.h"
+#include <esp_private/esp_clk.h>
 #endif
 
 #ifndef _ASMLANGUAGE
 
 void __esp_platform_start(void);
 
+static inline uint32_t esp_core_id(void)
+{
+	return 0;
+}
+
 extern void esp_rom_intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num);
 extern void esp_rom_uart_attach(void);
 extern void esp_rom_uart_tx_wait_idle(uint8_t uart_no);
@@ -40,7 +45,6 @@ extern int esp_rom_Cache_Dbus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t
 extern int esp_rom_Cache_Ibus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr,
 				uint32_t psize, uint32_t num, uint32_t fixed);
 extern void esp_rom_Cache_Resume_ICache(uint32_t autoload);
-extern spiflash_legacy_data_t esp_rom_spiflash_legacy_data;
 extern int esp_rom_gpio_matrix_in(uint32_t gpio, uint32_t signal_index,
 				    bool inverted);
 extern int esp_rom_gpio_matrix_out(uint32_t gpio, uint32_t signal_index,

soc/espressif/esp32c3/soc_irq.c

@@ -6,11 +6,10 @@
 
 #include <soc/rtc_cntl_reg.h>
 #include <soc/timer_group_reg.h>
+#include <soc/ext_mem_defs.h>
 #include <soc/gpio_reg.h>
 #include <soc/syscon_reg.h>
 #include <soc/system_reg.h>
-#include <soc/cache_memory.h>
-#include "hal/soc_ll.h"
 #include <riscv/interrupt.h>
 #include <soc/interrupt_reg.h>
 #include <soc/periph_defs.h>