serial: atmel_sam3: remove driver as it was deprecated
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala
Kumar Gala
parent
034b458141
commit
ace47887bd
7 changed files with 0 additions and 326 deletions
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@ -9,16 +9,6 @@ if BOARD_ARDUINO_DUE
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config BOARD
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config BOARD
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default arduino_due
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default arduino_due
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if UART_ATMEL_SAM3
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config UART_ATMEL_SAM3_BAUD_RATE
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default 115200
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config UART_ATMEL_SAM3_CLK_FREQ
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default 84000000
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endif # UART_ATMEL_SAM3
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if GPIO
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if GPIO
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config GPIO_ATMEL_SAM3
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config GPIO_ATMEL_SAM3
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@ -75,8 +75,6 @@ source "drivers/serial/Kconfig.stellaris"
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source "drivers/serial/Kconfig.nsim"
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source "drivers/serial/Kconfig.nsim"
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source "drivers/serial/Kconfig.atmel_sam3"
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source "drivers/serial/Kconfig.usart_sam"
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source "drivers/serial/Kconfig.usart_sam"
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source "drivers/serial/Kconfig.uart_sam"
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source "drivers/serial/Kconfig.uart_sam"
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@ -1,36 +0,0 @@
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menuconfig UART_ATMEL_SAM3
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bool "[deprecated] Atmel SAM3 family processor UART driver"
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default n
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select SERIAL_HAS_DRIVER
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depends on SOC_SERIES_SAM3X
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help
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This driver is deprecated and will be removed. Use
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"Atmel SAM MCU family UART driver" instead.
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This option enables the UART driver for Atmel SAM3
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family processors. Note that there is only one
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UART controller on SAM3. It has only two wires
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for RX and TX, and does not have other pins
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(such as CTS and RTS).
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config UART_ATMEL_SAM3_IRQ_PRI
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int "Atmel SAM3 UART Interrupt Priority"
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default 0
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depends on UART_ATMEL_SAM3
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help
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The interrupt priority for UART port.
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config UART_ATMEL_SAM3_BAUD_RATE
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int "Atmel SAM3 UART Baud Rate"
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default 0
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depends on UART_ATMEL_SAM3
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help
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The baud rate for UART port to be set to at boot.
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config UART_ATMEL_SAM3_CLK_FREQ
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int "Atmel SAM3 UART Clock Frequency"
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default 0
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depends on UART_ATMEL_SAM3
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help
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The clock frequency for UART port.
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@ -7,7 +7,6 @@ obj-$(CONFIG_UART_MCUX_LPSCI) += uart_mcux_lpsci.o
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obj-$(CONFIG_UART_MCUX_LPUART) += uart_mcux_lpuart.o
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obj-$(CONFIG_UART_MCUX_LPUART) += uart_mcux_lpuart.o
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obj-$(CONFIG_UART_STELLARIS) += uart_stellaris.o
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obj-$(CONFIG_UART_STELLARIS) += uart_stellaris.o
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obj-$(CONFIG_UART_NSIM) += uart_nsim.o
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obj-$(CONFIG_UART_NSIM) += uart_nsim.o
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obj-$(CONFIG_UART_ATMEL_SAM3) += uart_atmel_sam3.o
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obj-$(CONFIG_UART_SAM) += uart_sam.o
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obj-$(CONFIG_UART_SAM) += uart_sam.o
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obj-$(CONFIG_USART_SAM) += usart_sam.o
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obj-$(CONFIG_USART_SAM) += usart_sam.o
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obj-$(CONFIG_UART_QMSI) += uart_qmsi.o
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obj-$(CONFIG_UART_QMSI) += uart_qmsi.o
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@ -1,246 +0,0 @@
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/*
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* Copyright (c) 2016 Intel Corporation.
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* Copyright (c) 2013-2015 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @brief Driver for UART on Atmel SAM3 family processor.
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*
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* Note that there is only one UART controller on the SoC.
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* It has two wires for RX and TX, and does not have other such as
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* CTS or RTS. Also, the RX and TX are connected directly to
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* bit shifters and there is no FIFO.
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*
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* For full serial function, use the USART controller.
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*
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* (used uart_stellaris.c as template)
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*/
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#include <kernel.h>
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#include <arch/cpu.h>
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#include <misc/__assert.h>
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#include <board.h>
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#include <init.h>
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#include <uart.h>
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#include <linker/sections.h>
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/* UART registers struct */
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struct _uart {
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/* UART registers */
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u32_t cr; /* 0x00 Control Register */
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u32_t mr; /* 0x04 Mode Register */
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u32_t ier; /* 0x08 Interrupt Enable Register */
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u32_t idr; /* 0x0C Interrupt Disable Register */
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u32_t imr; /* 0x10 Interrupt Mask Register */
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u32_t sr; /* 0x14 Status Register */
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u32_t rhr; /* 0x18 Receive Holding Register */
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u32_t thr; /* 0x1C Transmit Holding Register */
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u32_t brgr; /* 0x20 Baud Rate Generator Register */
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u32_t reserved[55]; /* 0x24 - 0xFF */
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/* PDC related registers */
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u32_t pdc_rpr; /* 0x100 Receive Pointer Reg */
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u32_t pdc_rcr; /* 0x104 Receive Counter Reg */
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u32_t pdc_tpr; /* 0x108 Transmit Pointer Reg */
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u32_t pdc_tcr; /* 0x10C Transmit Counter Reg */
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u32_t pdc_rnpr; /* 0x110 Receive Next Pointer */
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u32_t pdc_rncr; /* 0x114 Receive Next Counter */
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u32_t pdc_tnpr; /* 0x118 Transmit Next Pointer */
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u32_t pdc_tncr; /* 0x11C Transmit Next Counter */
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u32_t pdc_ptcr; /* 0x120 Transfer Control Reg */
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u32_t pdc_ptsr; /* 0x124 Transfer Status Reg */
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};
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/* Device data structure */
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struct uart_sam3_dev_data_t {
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u32_t baud_rate; /* Baud rate */
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};
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/* convenience defines */
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#define DEV_CFG(dev) \
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((const struct uart_device_config * const)(dev)->config->config_info)
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#define DEV_DATA(dev) \
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((struct uart_sam3_dev_data_t * const)(dev)->driver_data)
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#define UART_STRUCT(dev) \
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((volatile struct _uart *)(DEV_CFG(dev))->base)
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/* Registers */
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#define UART_CR(dev) (*((volatile u32_t *)(DEV_CFG(dev)->base + 0x00)))
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#define UART_MR(dev) (*((volatile u32_t *)(DEV_CFG(dev)->base + 0x04)))
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#define UART_IER(dev) (*((volatile u32_t *)(DEV_CFG(dev)->base + 0x08)))
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#define UART_IDR(dev) (*((volatile u32_t *)(DEV_CFG(dev)->base + 0x0C)))
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#define UART_IMR(dev) (*((volatile u32_t *)(DEV_CFG(dev)->base + 0x10)))
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#define UART_SR(dev) (*((volatile u32_t *)(DEV_CFG(dev)->base + 0x14)))
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#define UART_RHR(dev) (*((volatile u32_t *)(DEV_CFG(dev)->base + 0x18)))
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#define UART_THR(dev) (*((volatile u32_t *)(DEV_CFG(dev)->base + 0x1C)))
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#define UART_BRGR(dev) (*((volatile u32_t *)(DEV_CFG(dev)->base + 0x20)))
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/* bits */
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#define UART_MR_PARTIY_MASK (0x0E00)
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#define UART_MR_PARITY_EVEN (0 << 9)
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#define UART_MR_PARITY_ODD (1 << 9)
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#define UART_MR_PARITY_SPACE (2 << 9)
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#define UART_MR_PARITY_MARK (3 << 9)
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#define UART_MR_PARITY_NO (4 << 9)
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#define UART_MR_CHMODE_MASK (0xC000)
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#define UART_INT_RXRDY (1 << 0)
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#define UART_INT_TXRDY (1 << 1)
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#define UART_INT_ENDRX (1 << 3)
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#define UART_INT_ENDTX (1 << 4)
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#define UART_INT_OVRE (1 << 5)
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#define UART_INT_FRAME (1 << 6)
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#define UART_INT_PARE (1 << 7)
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#define UART_INT_TXEMPTY (1 << 9)
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#define UART_INT_TXBUFE (1 << 11)
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#define UART_INT_RXBUFF (1 << 12)
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#define UART_PDC_PTCR_RXTDIS (1 << 1)
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#define UART_PDC_PTCR_TXTDIS (1 << 9)
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static const struct uart_driver_api uart_sam3_driver_api;
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/**
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* @brief Set the baud rate
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*
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* This routine set the given baud rate for the UART.
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*
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* @param dev UART device struct
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* @param baudrate Baud rate
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* @param sys_clk_freq_hz System clock frequency in Hz
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*
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* @return N/A
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*/
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static void baudrate_set(struct device *dev,
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u32_t baudrate, u32_t sys_clk_freq_hz)
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{
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volatile struct _uart *uart = UART_STRUCT(dev);
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const struct uart_device_config * const dev_cfg = DEV_CFG(dev);
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struct uart_sam3_dev_data_t * const dev_data = DEV_DATA(dev);
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u32_t divisor; /* baud rate divisor */
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ARG_UNUSED(sys_clk_freq_hz);
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if ((baudrate != 0) && (dev_cfg->sys_clk_freq != 0)) {
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/* calculate baud rate divisor */
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divisor = (dev_cfg->sys_clk_freq / baudrate) >> 4;
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divisor &= 0xFFFF;
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uart->brgr = divisor;
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dev_data->baud_rate = baudrate;
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}
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}
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/**
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* @brief Initialize UART channel
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*
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* This routine is called to reset the chip in a quiescent state.
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* It is assumed that this function is called only once per UART.
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*
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* @deprecated This driver will be deprecated. Please use uart_sam.c,
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* SAM family driver instead.
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*
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* @param dev UART device struct
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*
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* @return 0
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*/
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static int __deprecated uart_sam3_init(struct device *dev)
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{
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volatile struct _uart *uart = UART_STRUCT(dev);
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/* Enable UART clock in PMC */
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PMC->PMC_PCER0 = (1 << ID_UART);
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/* Detach pins PA8 and PA9 from PIO controller */
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PIOA->PIO_PDR = (1 << 8) | (1 << 9);
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/* Disable PDC (DMA) */
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uart->pdc_ptcr = UART_PDC_PTCR_RXTDIS | UART_PDC_PTCR_TXTDIS;
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/* Reset and disable UART */
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uart->cr = UART_CR_RSTRX | UART_CR_RSTTX
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| UART_CR_RXDIS | UART_CR_TXDIS | UART_CR_RSTSTA;
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/* No parity and normal mode */
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uart->mr = UART_MR_PARITY_NO | UART_MR_CHMODE_NORMAL;
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/* Set baud rate */
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baudrate_set(dev, DEV_DATA(dev)->baud_rate,
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DEV_CFG(dev)->sys_clk_freq);
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/* Enable receiver and transmitter */
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uart->cr = UART_CR_RXEN | UART_CR_TXEN;
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return 0;
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}
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/**
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* @brief Poll the device for input.
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*
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* @param dev UART device struct
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* @param c Pointer to character
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*
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* @return 0 if a character arrived, -1 if the input buffer if empty.
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*/
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static int uart_sam3_poll_in(struct device *dev, unsigned char *c)
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{
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volatile struct _uart *uart = UART_STRUCT(dev);
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if (!(uart->sr & UART_INT_RXRDY))
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return (-1);
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/* got a character */
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*c = (unsigned char)uart->rhr;
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return 0;
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}
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/**
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* @brief Output a character in polled mode.
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*
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* Checks if the transmitter is empty. If empty, a character is written to
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* the data register.
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*
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* @param dev UART device struct
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* @param c Character to send
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*
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* @return Sent character
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*/
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static unsigned char uart_sam3_poll_out(struct device *dev,
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unsigned char c)
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{
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volatile struct _uart *uart = UART_STRUCT(dev);
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/* Wait for transmitter to be ready */
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while (!(uart->sr & UART_INT_TXRDY))
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;
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/* send a character */
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uart->thr = (u32_t)c;
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return c;
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}
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static const struct uart_driver_api uart_sam3_driver_api = {
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.poll_in = uart_sam3_poll_in,
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.poll_out = uart_sam3_poll_out,
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};
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static const struct uart_device_config uart_sam3_dev_cfg_0 = {
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.base = (u8_t *)UART,
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.sys_clk_freq = CONFIG_UART_ATMEL_SAM3_CLK_FREQ,
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};
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static struct uart_sam3_dev_data_t uart_sam3_dev_data_0 = {
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.baud_rate = CONFIG_UART_ATMEL_SAM3_BAUD_RATE,
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};
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DEVICE_AND_API_INIT(uart_sam3_0, CONFIG_UART_ATMEL_SAM3_NAME, &uart_sam3_init,
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&uart_sam3_dev_data_0, &uart_sam3_dev_cfg_0,
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PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&uart_sam3_driver_api);
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#define CONFIG_I2C_1_IRQ_PRI ATMEL_SAM_I2C_TWI_40090000_IRQ_0_PRIORITY
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#define CONFIG_I2C_1_IRQ_PRI ATMEL_SAM_I2C_TWI_40090000_IRQ_0_PRIORITY
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#define CONFIG_I2C_1_PERIPHERAL_ID ATMEL_SAM_I2C_TWI_40090000_PERIPHERAL_ID
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#define CONFIG_I2C_1_PERIPHERAL_ID ATMEL_SAM_I2C_TWI_40090000_PERIPHERAL_ID
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#define CONFIG_UART_ATMEL_SAM3_NAME ATMEL_SAM_UART_400E0800_LABEL
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#define CONFIG_UART_SAM_PORT_0_NAME ATMEL_SAM_UART_400E0800_LABEL
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#define CONFIG_UART_SAM_PORT_0_NAME ATMEL_SAM_UART_400E0800_LABEL
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#define CONFIG_UART_SAM_PORT_0_BAUD_RATE ATMEL_SAM_UART_400E0800_CURRENT_SPEED
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#define CONFIG_UART_SAM_PORT_0_BAUD_RATE ATMEL_SAM_UART_400E0800_CURRENT_SPEED
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@ -1,30 +0,0 @@
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---
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title: SAM3X UART
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id: atmel,sam3x-uart
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version: 0.1
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description: >
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This binding gives a base representation of the SAM3X UART
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inherits:
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- !include uart.yaml
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properties:
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- compatible:
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type: string
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category: required
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description: compatible strings
|
|
||||||
constraint: "atmel,sam3x-uart"
|
|
||||||
|
|
||||||
- reg:
|
|
||||||
type: array
|
|
||||||
description: mmio register space
|
|
||||||
generation: define
|
|
||||||
category: required
|
|
||||||
|
|
||||||
- interrupts:
|
|
||||||
type: array
|
|
||||||
category: required
|
|
||||||
description: required interrupts
|
|
||||||
generation: define
|
|
||||||
...
|
|
||||||
Loading…
Add table
Add a link
Reference in a new issue