code_relocation: Extend the nocopy sample to nRF5340dk
The nRF5340dk is shipping an external QSPI flash that can be used to do XIP from. Extend the code_relocation nocopy sample to support this platform so that part of the functions are executed from internal flash and others from external flash. Signed-off-by: Carlo Caione <ccaione@baylibre.com>
This commit is contained in:
Carlo Caione
Anas Nashif
parent
d3203dc70d
commit
ac6060f966
8 changed files with 173 additions and 2 deletions
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@ -7,6 +7,7 @@ project(code_relocation_nocopy)
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FILE(GLOB app_sources src/*.c)
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target_sources(app PRIVATE ${app_sources})
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target_sources_ifdef(CONFIG_NRFX_QSPI app PRIVATE boards/nrf5340dk_nrf5340_cpuapp/ext_mem_init.c)
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# Run ext_code from the external flash (XIP). No need to copy.
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zephyr_code_relocate(src/ext_code.c EXTFLASH_TEXT NOCOPY)
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@ -11,3 +11,36 @@ using a custom linker script.
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Differently from the code relocation sample, this sample is relocating the
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content of the ext_code.c file to a different FLASH section and the code is XIP
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directly from there without the need to copy / relocate the code.
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nRF5340dk platform instructions
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*******************************
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The nRF5340 PDK has a 64 Mb external flash memory supporting Quad SPI. It is
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possible to do XIP from the external flash memory.
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The external flash memory is mapped to 0x10000000.
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In this sample we relocate some of the code to the external flash memory with
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the remaining Zephyr kernel in the internal flash.
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Compile the code:
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$ west build -b nrf5340dk_nrf5340_cpuapp samples/application_development/code_relocation_nocopy --pristine
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Get the HEX file from the ELF:
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$ arm-linux-gnueabihf-objcopy -O ihex build/zephyr/zephyr.elf zephyr.hex
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Erase the external FLASH (just to be sure):
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$ nrfjprog --qspicustominit --qspieraseall
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Write the HEX to internal and external FLASH:
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$ nrfjprog --coprocessor CP_APPLICATION --sectorerase --qspisectorerase --program zephyr.hex
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Execution output:
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*** Booting Zephyr OS build v3.0.0-rc3-25-g0df32cec1ff2 ***
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Address of main function 0x4f9
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Address of function_in_ext_flash 0x10000001
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Address of var_ext_sram_data 0x200000a0 (10)
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Address of function_in_sram 0x20000001
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Address of var_sram_data 0x200000a4 (10)
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Hello World! nrf5340dk_nrf5340_cpuapp
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@ -0,0 +1,3 @@
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CONFIG_NRFX_QSPI=y
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CONFIG_GPIO=y
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CONFIG_NRF_ENABLE_CACHE=n
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@ -0,0 +1,112 @@
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/*
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* Copyright (c) 2022 Nordic Semiconductor ASA.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <errno.h>
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#include <init.h>
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#include <zephyr.h>
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#include <device.h>
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#include <nrfx_qspi.h>
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#include <hal/nrf_clock.h>
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#define QSPI_STD_CMD_WRSR 0x01
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#define QSPI_STD_CMD_WRDI 0x04
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#define QSPI_STD_CMD_RSTEN 0x66
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#define QSPI_STD_CMD_RST 0x99
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#define QSPI_NODE DT_NODELABEL(qspi)
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#define QSPI_PROP_AT(prop, idx) DT_PROP_BY_IDX(QSPI_NODE, prop, idx)
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static inline int qspi_get_zephyr_ret_code(nrfx_err_t res)
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{
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switch (res) {
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case NRFX_SUCCESS:
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return 0;
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case NRFX_ERROR_INVALID_PARAM:
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case NRFX_ERROR_INVALID_ADDR:
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return -EINVAL;
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case NRFX_ERROR_INVALID_STATE:
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return -ECANCELED;
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case NRFX_ERROR_BUSY:
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case NRFX_ERROR_TIMEOUT:
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default:
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return -EBUSY;
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}
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}
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static int qspi_ext_mem_init(const struct device *dev)
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{
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ARG_UNUSED(dev);
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int ret;
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nrf_clock_hfclk192m_div_set(NRF_CLOCK, NRF_CLOCK_HFCLK_DIV_1);
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static nrfx_qspi_config_t qspi_config = {
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.pins = {
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.sck_pin = DT_PROP(QSPI_NODE, sck_pin),
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.csn_pin = QSPI_PROP_AT(csn_pins, 0),
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.io0_pin = QSPI_PROP_AT(io_pins, 0),
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.io1_pin = QSPI_PROP_AT(io_pins, 1),
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.io2_pin = QSPI_PROP_AT(io_pins, 2),
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.io3_pin = QSPI_PROP_AT(io_pins, 3),
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},
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.irq_priority = NRFX_QSPI_DEFAULT_CONFIG_IRQ_PRIORITY,
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.prot_if = {
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.readoc = NRF_QSPI_READOC_READ4IO,
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.writeoc = NRF_QSPI_WRITEOC_PP4IO,
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.addrmode = NRF_QSPI_ADDRMODE_24BIT,
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.dpmconfig = false
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},
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.phy_if = {
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.sck_freq = 1,
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.sck_delay = 0x05,
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.spi_mode = NRF_QSPI_MODE_0,
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.dpmen = false
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}
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};
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nrfx_err_t res = nrfx_qspi_init(&qspi_config, NULL, NULL);
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ret = qspi_get_zephyr_ret_code(res);
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if (ret < 0) {
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return ret;
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}
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/* Enable XiP */
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nrf_qspi_xip_set(NRF_QSPI, true);
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uint8_t temporary = 0x40;
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nrf_qspi_cinstr_conf_t cinstr_cfg = {
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.opcode = QSPI_STD_CMD_RSTEN,
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.length = NRF_QSPI_CINSTR_LEN_1B,
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.io2_level = true,
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.io3_level = true,
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.wipwait = true,
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.wren = true
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};
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/* Send reset enable */
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nrfx_qspi_cinstr_xfer(&cinstr_cfg, NULL, NULL);
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/* Send reset command */
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cinstr_cfg.opcode = QSPI_STD_CMD_RST;
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nrfx_qspi_cinstr_xfer(&cinstr_cfg, NULL, NULL);
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/* Switch to qspi mode and high performance */
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cinstr_cfg.opcode = QSPI_STD_CMD_WRSR;
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cinstr_cfg.length = NRF_QSPI_CINSTR_LEN_2B;
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nrfx_qspi_cinstr_xfer(&cinstr_cfg, &temporary, NULL);
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/* Send write disable command */
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cinstr_cfg.opcode = QSPI_STD_CMD_WRDI;
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cinstr_cfg.wren = false;
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cinstr_cfg.length = NRF_QSPI_CINSTR_LEN_1B;
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nrfx_qspi_cinstr_xfer(&cinstr_cfg, NULL, NULL);
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return 0;
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}
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SYS_INIT(qspi_ext_mem_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_OBJECTS);
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@ -18,6 +18,19 @@
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#include <linker/linker-defs.h>
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#include <linker/linker-tool.h>
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#if CONFIG_BOARD_NRF5340DK_NRF5340_CPUAPP
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/*
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* nRF5340dk is shipping a QSPI external flash mapped at 0x1000_0000 that can
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* be used for XIP
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*/
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MEMORY
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{
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EXTFLASH (wx) : ORIGIN = 0x10000000, LENGTH = 0x800000
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}
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#else
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/*
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* Add another fake portion of FLASH to simulate a secondary or external FLASH
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* that we can do XIP from.
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@ -30,4 +43,6 @@ MEMORY
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EXTFLASH (wx) : ORIGIN = 0x5000, LENGTH = EXTFLASH_SIZE
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}
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#endif /* CONFIG_BOARD_NRF5340DK_NRF5340_CPUAPP */
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#include <arch/arm/aarch32/cortex_m/scripts/linker.ld>
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@ -3,3 +3,4 @@ CONFIG_HAVE_CUSTOM_LINKER_SCRIPT=y
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CONFIG_CUSTOM_LINKER_SCRIPT="linker_arm_nocopy.ld"
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CONFIG_COVERAGE=n
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CONFIG_XIP=y
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CONFIG_LOG=y
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@ -3,7 +3,7 @@ sample:
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name: code relocation nocopy
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tests:
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sample.application_development.code_relocation_nocopy:
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platform_allow: qemu_cortex_m3
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platform_allow: qemu_cortex_m3 nrf5340dk_nrf5340_cpuapp
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tags: linker
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harness: console
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harness_config:
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@ -27,12 +27,18 @@ void disable_mpu_rasr_xn(void)
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*/
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for (index = 0U; index < 8; index++) {
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MPU->RNR = index;
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#if defined(CONFIG_ARMV8_M_BASELINE) || defined(CONFIG_ARMV8_M_MAINLINE)
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if (MPU->RBAR & MPU_RBAR_XN_Msk) {
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MPU->RBAR ^= MPU_RBAR_XN_Msk;
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}
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#else
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if (MPU->RASR & MPU_RASR_XN_Msk) {
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MPU->RASR ^= MPU_RASR_XN_Msk;
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}
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#endif /* CONFIG_ARMV8_M_BASELINE || CONFIG_ARMV8_M_MAINLINE */
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}
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}
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#endif /* CONFIG_ARM_MPU */
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#endif /* CONFIG_ARM_MPU */
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extern void function_in_ext_flash(void);
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extern void function_in_sram(void);
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