diff --git a/boards/nordic/nrf54l15dk/Kconfig.defconfig b/boards/nordic/nrf54l15dk/Kconfig.defconfig new file mode 100644 index 00000000000..2b753df3515 --- /dev/null +++ b/boards/nordic/nrf54l15dk/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF54L15DK_NRF54L15_CPUAPP + +config BT_CTLR + default BT + +config ROM_START_OFFSET + default 0x800 if BOOTLOADER_MCUBOOT + +endif # BOARD_NRF54L15DK_NRF54L15_CPUAPP diff --git a/boards/nordic/nrf54l15dk/Kconfig.nrf54l15dk b/boards/nordic/nrf54l15dk/Kconfig.nrf54l15dk new file mode 100644 index 00000000000..e385ef84f89 --- /dev/null +++ b/boards/nordic/nrf54l15dk/Kconfig.nrf54l15dk @@ -0,0 +1,7 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF54L15DK + select SOC_NRF54L15_CPUAPP if BOARD_NRF54L15DK_NRF54L15_CPUAPP + select SOC_NRF54L15_CPUFLPR if BOARD_NRF54L15DK_NRF54L15_CPUFLPR || \ + BOARD_NRF54L15DK_NRF54L15_CPUFLPR_XIP diff --git a/boards/nordic/nrf54l15dk/board.cmake b/boards/nordic/nrf54l15dk/board.cmake new file mode 100644 index 00000000000..1fd92b7fced --- /dev/null +++ b/boards/nordic/nrf54l15dk/board.cmake @@ -0,0 +1,11 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_SOC_NRF54L15_CPUAPP) + board_runner_args(jlink "--device=cortex-m33" "--speed=4000") +elseif(CONFIG_SOC_NRF54L15_CPUFLPR) + board_runner_args(jlink "--speed=4000") +endif() + +include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/nordic/nrf54l15dk/board.yml b/boards/nordic/nrf54l15dk/board.yml new file mode 100644 index 00000000000..7a8bf2f5cf1 --- /dev/null +++ b/boards/nordic/nrf54l15dk/board.yml @@ -0,0 +1,8 @@ +board: + name: nrf54l15dk + vendor: nordic + socs: + - name: nrf54l15 + variants: + - name: xip + cpucluster: cpuflpr diff --git a/boards/nordic/nrf54l15dk/doc/img/nrf54l15dk_nrf54l15.webp b/boards/nordic/nrf54l15dk/doc/img/nrf54l15dk_nrf54l15.webp new file mode 100644 index 00000000000..bac57d69e62 Binary files /dev/null and b/boards/nordic/nrf54l15dk/doc/img/nrf54l15dk_nrf54l15.webp differ diff --git a/boards/nordic/nrf54l15dk/doc/index.rst b/boards/nordic/nrf54l15dk/doc/index.rst new file mode 100644 index 00000000000..6980076d954 --- /dev/null +++ b/boards/nordic/nrf54l15dk/doc/index.rst @@ -0,0 +1,145 @@ +.. _nrf54l15dk_nrf54l15: + +nRF54L15 DK +############ + +Overview +******** + +.. note:: + + All software for the nRF54L15 SoC is experimental and hardware availability + is restricted to the participants in the limited sampling program. + +The nRF54L15 Development Kit hardware provides support for the Nordic Semiconductor +nRF54L15 Arm Cortex-M33 CPU and the following devices: + +* :abbr:`SAADC (Successive Approximation Analog to Digital Converter)` +* CLOCK +* RRAM +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`TWIM (I2C-compatible two-wire interface master with EasyDMA)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* :abbr:`GRTC (Global real-time counter)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UARTE (Universal asynchronous receiver-transmitter)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/nrf54l15dk_nrf54l15.webp + :align: center + :alt: nRF54L15 DK + + nRF54L15 DK (Credit: Nordic Semiconductor) + +Hardware +******** + +nRF54L15 DK has two crystal oscillators: + +* High-frequency 32 MHz crystal oscillator (HFXO) +* Low-frequency 32.768 kHz crystal oscillator (LFXO) + +The crystal oscillators can be configured to use either +internal or external capacitors. + +Supported Features +================== + +The ``nrf54l15dk/nrf54l15/cpuapp`` board target configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| GRTC | on-chip | counter | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RRAM | on-chip | flash | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SAADC | on-chip | adc | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| SPU | on-chip | system protection | ++-----------+------------+----------------------+ +| TWIM | on-chip | i2c | ++-----------+------------+----------------------+ +| UARTE | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. + +Programming and Debugging +************************* + +Applications for the ``nrf54l15dk/nrf54l15/cpuapp`` board target can be +built, flashed, and debugged in the usual way. See +:ref:`build_an_application` and :ref:`application_run` for more details on +building and running. + +Applications for the ``nrf54l15dk/nrf54l15/cpuflpr`` board target need +to be build as multicore configuration with code snippet called ``vpr_launcher`` +for the application core. + +Enter the following command to compile ``hello_world`` for the FLPR core:: + west build -p -b nrf54l15pdk/nrf54l15/cpuflpr --sysbuild -- -DSB_VPR_LAUNCHER=y + +Flashing +======== + +As an example, this section shows how to build and flash the :ref:`hello_world` +application. + +.. warning:: + + When programming the device, you might get an error similar to the following message:: + + ERROR: The operation attempted is unavailable due to readback protection in + ERROR: your device. Please use --recover to unlock the device. + + This error occurs when readback protection is enabled. + To disable the readback protection, you must *recover* your device. + + Enter the following command to recover the core:: + + west flash --recover + + The ``--recover`` command erases the flash memory and then writes a small binary into + the recovered flash memory. + This binary prevents the readback protection from enabling itself again after a pin + reset or power cycle. + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. + +To build and program the sample to the nRF54L15 DK, complete the following steps: + +First, connect the nRF54L15 DK to you computer using the IMCU USB port on the DK. +Next, build the sample by running the following command: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nrf54l15dk/nrf54l15/cpuapp + :goals: build flash + +Testing the LEDs and buttons in the nRF54L15 DK +************************************************ + +Test the nRF54L15 DK with a :zephyr:code-sample:`blinky` sample. diff --git a/boards/nordic/nrf54l15dk/nrf54l15_cpuapp_common.dtsi b/boards/nordic/nrf54l15dk/nrf54l15_cpuapp_common.dtsi new file mode 100644 index 00000000000..191babb632f --- /dev/null +++ b/boards/nordic/nrf54l15dk/nrf54l15_cpuapp_common.dtsi @@ -0,0 +1,156 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* This file is common to the secure and non-secure domain */ + +#include +#include "nrf54l15dk_nrf54l15-common.dtsi" + +/ { + chosen { + zephyr,console = &uart20; + zephyr,shell-uart = &uart20; + zephyr,uart-mcumgr = &uart20; + zephyr,bt-mon-uart = &uart20; + zephyr,bt-c2h-uart = &uart20; + zephyr,flash-controller = &rram_controller; + zephyr,flash = &cpuapp_rram; + zephyr,ieee802154 = &ieee802154; + }; +}; + +&cpuapp_sram { + status = "okay"; +}; + +&lfxo { + load-capacitors = "internal"; + load-capacitance-femtofarad = <15500>; +}; + +&hfxo { + load-capacitors = "internal"; + load-capacitance-femtofarad = <15000>; +}; + +®ulators { + status = "okay"; +}; + +&vregmain { + status = "okay"; + regulator-initial-mode = ; +}; + +&grtc { + owned-channels = <0 1 2 3 4 5 6 7 8 9 10 11>; + /* Channels 7-11 reserved for Zero Latency IRQs, 3-4 for FLPR */ + child-owned-channels = <3 4 7 8 9 10 11>; + status = "okay"; +}; + +&cpuapp_rram { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x0 DT_SIZE_K(64)>; + }; + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x10000 DT_SIZE_K(324)>; + }; + slot0_ns_partition: partition@61000 { + label = "image-0-nonsecure"; + reg = <0x61000 DT_SIZE_K(324)>; + }; + slot1_partition: partition@b2000 { + label = "image-1"; + reg = <0xb2000 DT_SIZE_K(324)>; + }; + slot1_ns_partition: partition@103000 { + label = "image-1-nonsecure"; + reg = <0x103000 DT_SIZE_K(324)>; + }; + /* 32k from 0x154000 to 0x15bfff reserved for TF-M partitions */ + storage_partition: partition@15c000 { + label = "storage"; + reg = <0x15c000 DT_SIZE_K(36)>; + }; + }; +}; + +&uart20 { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpiote20 { + status = "okay"; +}; + +&gpiote30 { + status = "okay"; +}; + +&radio { + status = "okay"; +}; + +&ieee802154 { + status = "okay"; +}; + +&temp { + status = "okay"; +}; + +&clock { + status = "okay"; +}; + +&spi00 { + status = "okay"; + cs-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&spi00_default>; + pinctrl-1 = <&spi00_sleep>; + pinctrl-names = "default", "sleep"; + + mx25r64: mx25r6435f@0 { + compatible = "jedec,spi-nor"; + status = "okay"; + reg = <0>; + spi-max-frequency = <8000000>; + jedec-id = [c2 28 17]; + sfdp-bfp = [ + e5 20 f1 ff ff ff ff 03 44 eb 08 6b 08 3b 04 bb + ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52 + 10 d8 00 ff 23 72 f5 00 82 ed 04 cc 44 83 48 44 + 30 b0 30 b0 f7 c4 d5 5c 00 be 29 ff f0 d0 ff ff + ]; + size = <67108864>; + has-dpd; + t-enter-dpd = <10000>; + t-exit-dpd = <35000>; + }; +}; + +&adc { + status = "okay"; +}; diff --git a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15-common.dtsi b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15-common.dtsi new file mode 100644 index 00000000000..02170276476 --- /dev/null +++ b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15-common.dtsi @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "nrf54l15dk_nrf54l15-pinctrl.dtsi" + +/ { + leds { + compatible = "gpio-leds"; + led0: led_0 { + gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>; + label = "Green LED 0"; + }; + led1: led_1 { + gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + label = "Green LED 1"; + }; + led2: led_2 { + gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; + label = "Green LED 2"; + }; + led3: led_3 { + gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; + label = "Green LED 3"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + /* + * PWM signal can be exposed on GPIO pin only within same domain. + * There is only one domain which contains both PWM and GPIO: + * PWM20/21/22 and GPIO Port P1. + * Only LEDs connected to P1 can work with PWM, for example LED1. + */ + pwm_led1: pwm_led_1 { + pwms = <&pwm20 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + }; + }; + + buttons { + compatible = "gpio-keys"; + button0: button_0 { + gpios = <&gpio1 13 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 0"; + zephyr,code = ; + }; + button1: button_1 { + gpios = <&gpio1 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 1"; + zephyr,code = ; + }; + button2: button_2 { + gpios = <&gpio1 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 2"; + zephyr,code = ; + }; + button3: button_3 { + gpios = <&gpio0 4 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 3"; + zephyr,code = ; + }; + }; + + aliases { + led0 = &led0; + led1 = &led1; + led2 = &led2; + led3 = &led3; + pwm-led0 = &pwm_led1; + sw0 = &button0; + sw1 = &button1; + sw2 = &button2; + sw3 = &button3; + watchdog0 = &wdt31; + }; +}; + +&uart20 { + current-speed = <115200>; + pinctrl-0 = <&uart20_default>; + pinctrl-1 = <&uart20_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&uart30 { + current-speed = <115200>; + pinctrl-0 = <&uart30_default>; + pinctrl-1 = <&uart30_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&pwm20 { + status = "okay"; + pinctrl-0 = <&pwm20_default>; + pinctrl-1 = <&pwm20_sleep>; + pinctrl-names = "default", "sleep"; +}; diff --git a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15-pinctrl.dtsi b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15-pinctrl.dtsi new file mode 100644 index 00000000000..0b6e2056a82 --- /dev/null +++ b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15-pinctrl.dtsi @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + /omit-if-no-ref/ uart20_default: uart20_default { + group1 { + psels = , + ; + }; + group2 { + psels = , + ; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ uart20_sleep: uart20_sleep { + group1 { + psels = , + , + , + ; + low-power-enable; + }; + }; + + /omit-if-no-ref/ uart30_default: uart30_default { + group1 { + psels = , + ; + }; + group2 { + psels = , + ; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ uart30_sleep: uart30_sleep { + group1 { + psels = , + , + , + ; + low-power-enable; + }; + }; + + /omit-if-no-ref/ spi00_default: spi00_default { + group1 { + psels = , + , + ; + }; + }; + + /omit-if-no-ref/ spi00_sleep: spi00_sleep { + group1 { + psels = , + , + ; + low-power-enable; + }; + }; + + /omit-if-no-ref/ pwm20_default: pwm20_default { + group1 { + psels = ; + }; + }; + + /omit-if-no-ref/ pwm20_sleep: pwm20_sleep { + group1 { + psels = ; + low-power-enable; + }; + }; +}; diff --git a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuapp.dts b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuapp.dts new file mode 100644 index 00000000000..b71f55c5fb4 --- /dev/null +++ b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuapp.dts @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include "nrf54l15_cpuapp_common.dtsi" + +/ { + compatible = "nordic,nrf54l15dk_nrf54l15-cpuapp"; + model = "Nordic nRF54L15 DK nRF54L15 Application MCU"; + + chosen { + zephyr,code-partition = &slot0_partition; + zephyr,sram = &cpuapp_sram; + }; +}; diff --git a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuapp.yaml b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuapp.yaml new file mode 100644 index 00000000000..a3ddb5db1c6 --- /dev/null +++ b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuapp.yaml @@ -0,0 +1,24 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +identifier: nrf54l15dk/nrf54l15/cpuapp +name: nRF54l15-DK-nRF54l15-Application +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +sysbuild: true +ram: 188 +flash: 324 +supported: + - adc + - counter + - gpio + - i2c + - pwm + - retained_mem + - spi + - watchdog + - i2s diff --git a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuapp_defconfig b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuapp_defconfig new file mode 100644 index 00000000000..02796a1361e --- /dev/null +++ b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuapp_defconfig @@ -0,0 +1,29 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# MPU-based null-pointer dereferencing detection cannot +# be applied as the (0x0 - 0x400) is unmapped for this target. +CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y + +# Enable Cache +CONFIG_CACHE_MANAGEMENT=y +CONFIG_EXTERNAL_CACHE=y + +# Start SYSCOUNTER on driver init +CONFIG_NRF_GRTC_START_SYSCOUNTER=y diff --git a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuflpr.dts b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuflpr.dts new file mode 100644 index 00000000000..472e3f2b8d3 --- /dev/null +++ b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuflpr.dts @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "nrf54l15dk_nrf54l15-common.dtsi" + +/ { + model = "Nordic nRF54L15 DK nRF54L15 FLPR MCU"; + compatible = "nordic,nrf54l15dk_nrf54l15-cpuflpr"; + + chosen { + zephyr,console = &uart30; + zephyr,shell-uart = &uart30; + zephyr,code-partition = &cpuflpr_code_partition; + zephyr,flash = &cpuflpr_rram; + zephyr,sram = &cpuflpr_sram; + }; +}; + +&cpuflpr_sram { + status = "okay"; + /* size must be increased due to booting from SRAM */ + reg = <0x20028000 DT_SIZE_K(96)>; + ranges = <0x0 0x20028000 0x18000>; +}; + +&cpuflpr_rram { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + cpuflpr_code_partition: partition@0 { + label = "image-0"; + reg = <0x0 DT_SIZE_K(96)>; + }; + }; +}; + +&grtc { + owned-channels = <3 4>; + status = "okay"; +}; + +&uart30 { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpiote20 { + status = "okay"; +}; + +&gpiote30 { + status = "okay"; +}; diff --git a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuflpr.yaml b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuflpr.yaml new file mode 100644 index 00000000000..927773e0d5a --- /dev/null +++ b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuflpr.yaml @@ -0,0 +1,18 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +identifier: nrf54l15dk/nrf54l15/cpuflpr +name: nRF54L15-DK-nRF54L15-Fast-Lightweight-Peripheral-Processor +type: mcu +arch: riscv +toolchain: + - zephyr +sysbuild: true +ram: 96 +flash: 96 +supported: + - counter + - gpio + - i2c + - spi + - watchdog diff --git a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuflpr_defconfig b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuflpr_defconfig new file mode 100644 index 00000000000..256ac9103b4 --- /dev/null +++ b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuflpr_defconfig @@ -0,0 +1,17 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable GPIO +CONFIG_GPIO=y + +CONFIG_USE_DT_CODE_PARTITION=y + +# Execute from SRAM +CONFIG_XIP=n diff --git a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuflpr_xip.dts b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuflpr_xip.dts new file mode 100644 index 00000000000..6855e091d3c --- /dev/null +++ b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuflpr_xip.dts @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "nrf54l15dk_nrf54l15_cpuflpr.dts" + +&cpuflpr_sram { + reg = <0x2002f000 DT_SIZE_K(68)>; + ranges = <0x0 0x2002f000 0x11000>; +}; diff --git a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuflpr_xip.yaml b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuflpr_xip.yaml new file mode 100644 index 00000000000..d82dea6491f --- /dev/null +++ b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuflpr_xip.yaml @@ -0,0 +1,18 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +identifier: nrf54l15dk/nrf54l15/cpuflpr/xip +name: nRF54L15-DK-nRF54L15-Fast-Lightweight-Peripheral-Processor (RRAM XIP) +type: mcu +arch: riscv +toolchain: + - zephyr +sysbuild: true +ram: 68 +flash: 96 +supported: + - counter + - gpio + - i2c + - spi + - watchdog diff --git a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuflpr_xip_defconfig b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuflpr_xip_defconfig new file mode 100644 index 00000000000..0a436a648b4 --- /dev/null +++ b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuflpr_xip_defconfig @@ -0,0 +1,15 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable GPIO +CONFIG_GPIO=y + +# Execute from RRAM +CONFIG_XIP=y