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drivers: Cleans variable scopes for STM32 drivers

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Fix the scope of some variables in various STM32 drivers including:
 - SDMMC
 - DMA
 - OSPI/QSPI Flash
 - Interrupt controller

The variables are set static instead of global and const if appropriate.

Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
This commit is contained in:
Guillaume Gautier 2022-10-10 11:32:54 +02:00 • committed by Carles Cufí
commit aba432348b
6 changed files with 21 additions and 19 deletions
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2
drivers/disk/sdmmc_stm32.c
View file

@ -46,7 +46,7 @@ typedef void (*irq_config_func_t)(const struct device *dev);
#if STM32_SDMMC_USE_DMA #if STM32_SDMMC_USE_DMA
uint32_t table_priority[] = { static const uint32_t table_priority[] = {
DMA_PRIORITY_LOW, DMA_PRIORITY_LOW,
DMA_PRIORITY_MEDIUM, DMA_PRIORITY_MEDIUM,
DMA_PRIORITY_HIGH, DMA_PRIORITY_HIGH,

4
drivers/dma/dma_stm32.c
View file

@ -52,13 +52,13 @@ LOG_MODULE_REGISTER(dma_stm32, CONFIG_DMA_LOG_LEVEL);
#endif #endif
#endif /* DT_NODE_HAS_STATUS(DT_DRV_INST(1), okay) */ #endif /* DT_NODE_HAS_STATUS(DT_DRV_INST(1), okay) */
static uint32_t table_m_size[] = { static const uint32_t table_m_size[] = {
LL_DMA_MDATAALIGN_BYTE, LL_DMA_MDATAALIGN_BYTE,
LL_DMA_MDATAALIGN_HALFWORD, LL_DMA_MDATAALIGN_HALFWORD,
LL_DMA_MDATAALIGN_WORD, LL_DMA_MDATAALIGN_WORD,
}; };
static uint32_t table_p_size[] = { static const uint32_t table_p_size[] = {
LL_DMA_PDATAALIGN_BYTE, LL_DMA_PDATAALIGN_BYTE,
LL_DMA_PDATAALIGN_HALFWORD, LL_DMA_PDATAALIGN_HALFWORD,
LL_DMA_PDATAALIGN_WORD, LL_DMA_PDATAALIGN_WORD,

6
drivers/dma/dma_stm32u5.c
View file

@ -28,19 +28,19 @@ LOG_MODULE_REGISTER(dma_stm32, CONFIG_DMA_LOG_LEVEL);
#define DMA_STM32_0_STREAM_COUNT 16 #define DMA_STM32_0_STREAM_COUNT 16
#endif /* DT_NODE_HAS_STATUS(DT_DRV_INST(0), okay) */ #endif /* DT_NODE_HAS_STATUS(DT_DRV_INST(0), okay) */
static uint32_t table_m_size[] = { static const uint32_t table_m_size[] = {
LL_DMA_SRC_DATAWIDTH_BYTE, LL_DMA_SRC_DATAWIDTH_BYTE,
LL_DMA_SRC_DATAWIDTH_HALFWORD, LL_DMA_SRC_DATAWIDTH_HALFWORD,
LL_DMA_SRC_DATAWIDTH_WORD, LL_DMA_SRC_DATAWIDTH_WORD,
}; };
static uint32_t table_p_size[] = { static const uint32_t table_p_size[] = {
LL_DMA_DEST_DATAWIDTH_BYTE, LL_DMA_DEST_DATAWIDTH_BYTE,
LL_DMA_DEST_DATAWIDTH_HALFWORD, LL_DMA_DEST_DATAWIDTH_HALFWORD,
LL_DMA_DEST_DATAWIDTH_WORD, LL_DMA_DEST_DATAWIDTH_WORD,
}; };
static uint32_t table_priority[4] = { static const uint32_t table_priority[4] = {
LL_DMA_LOW_PRIORITY_LOW_WEIGHT, LL_DMA_LOW_PRIORITY_LOW_WEIGHT,
LL_DMA_LOW_PRIORITY_MID_WEIGHT, LL_DMA_LOW_PRIORITY_MID_WEIGHT,
LL_DMA_LOW_PRIORITY_HIGH_WEIGHT, LL_DMA_LOW_PRIORITY_HIGH_WEIGHT,

6
drivers/flash/flash_stm32_ospi.c
View file

@ -49,20 +49,20 @@ LOG_MODULE_REGISTER(flash_stm32_ospi, CONFIG_FLASH_LOG_LEVEL);
#define SPI_NOR_WRITEOC_NONE 0xFF #define SPI_NOR_WRITEOC_NONE 0xFF
#if STM32_OSPI_USE_DMA #if STM32_OSPI_USE_DMA
uint32_t table_m_size[] = { static const uint32_t table_m_size[] = {
LL_DMA_MDATAALIGN_BYTE, LL_DMA_MDATAALIGN_BYTE,
LL_DMA_MDATAALIGN_HALFWORD, LL_DMA_MDATAALIGN_HALFWORD,
LL_DMA_MDATAALIGN_WORD, LL_DMA_MDATAALIGN_WORD,
}; };
uint32_t table_p_size[] = { static const uint32_t table_p_size[] = {
LL_DMA_PDATAALIGN_BYTE, LL_DMA_PDATAALIGN_BYTE,
LL_DMA_PDATAALIGN_HALFWORD, LL_DMA_PDATAALIGN_HALFWORD,
LL_DMA_PDATAALIGN_WORD, LL_DMA_PDATAALIGN_WORD,
}; };
/* Lookup table to set dma priority from the DTS */ /* Lookup table to set dma priority from the DTS */
uint32_t table_priority[] = { static const uint32_t table_priority[] = {
DMA_PRIORITY_LOW, DMA_PRIORITY_LOW,
DMA_PRIORITY_MEDIUM, DMA_PRIORITY_MEDIUM,
DMA_PRIORITY_HIGH, DMA_PRIORITY_HIGH,

8
drivers/flash/flash_stm32_qspi.c
View file

@ -49,25 +49,27 @@ LOG_MODULE_REGISTER(flash_stm32_qspi, CONFIG_FLASH_LOG_LEVEL);
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_qspi_nor) #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_qspi_nor)
uint32_t table_m_size[] = { #if STM32_QSPI_USE_DMA
static const uint32_t table_m_size[] = {
LL_DMA_MDATAALIGN_BYTE, LL_DMA_MDATAALIGN_BYTE,
LL_DMA_MDATAALIGN_HALFWORD, LL_DMA_MDATAALIGN_HALFWORD,
LL_DMA_MDATAALIGN_WORD, LL_DMA_MDATAALIGN_WORD,
}; };
uint32_t table_p_size[] = { static const uint32_t table_p_size[] = {
LL_DMA_PDATAALIGN_BYTE, LL_DMA_PDATAALIGN_BYTE,
LL_DMA_PDATAALIGN_HALFWORD, LL_DMA_PDATAALIGN_HALFWORD,
LL_DMA_PDATAALIGN_WORD, LL_DMA_PDATAALIGN_WORD,
}; };
/* Lookup table to set dma priority from the DTS */ /* Lookup table to set dma priority from the DTS */
uint32_t table_priority[] = { static const uint32_t table_priority[] = {
DMA_PRIORITY_LOW, DMA_PRIORITY_LOW,
DMA_PRIORITY_MEDIUM, DMA_PRIORITY_MEDIUM,
DMA_PRIORITY_HIGH, DMA_PRIORITY_HIGH,
DMA_PRIORITY_VERY_HIGH, DMA_PRIORITY_VERY_HIGH,
}; };
#endif /* STM32_QSPI_USE_DMA */
typedef void (*irq_config_func_t)(const struct device *dev); typedef void (*irq_config_func_t)(const struct device *dev);

14
drivers/interrupt_controller/intc_exti_stm32.c
View file

@ -31,7 +31,7 @@
#if defined(CONFIG_SOC_SERIES_STM32F0X) || \ #if defined(CONFIG_SOC_SERIES_STM32F0X) || \
defined(CONFIG_SOC_SERIES_STM32L0X) || \ defined(CONFIG_SOC_SERIES_STM32L0X) || \
defined(CONFIG_SOC_SERIES_STM32G0X) defined(CONFIG_SOC_SERIES_STM32G0X)
const IRQn_Type exti_irq_table[] = { static const IRQn_Type exti_irq_table[] = {
EXTI0_1_IRQn, EXTI0_1_IRQn, EXTI2_3_IRQn, EXTI2_3_IRQn, EXTI0_1_IRQn, EXTI0_1_IRQn, EXTI2_3_IRQn, EXTI2_3_IRQn,
EXTI4_15_IRQn, EXTI4_15_IRQn, EXTI4_15_IRQn, EXTI4_15_IRQn, EXTI4_15_IRQn, EXTI4_15_IRQn, EXTI4_15_IRQn, EXTI4_15_IRQn,
EXTI4_15_IRQn, EXTI4_15_IRQn, EXTI4_15_IRQn, EXTI4_15_IRQn, EXTI4_15_IRQn, EXTI4_15_IRQn, EXTI4_15_IRQn, EXTI4_15_IRQn,
@ -44,21 +44,21 @@ const IRQn_Type exti_irq_table[] = {
defined(CONFIG_SOC_SERIES_STM32WBX) || \ defined(CONFIG_SOC_SERIES_STM32WBX) || \
defined(CONFIG_SOC_SERIES_STM32G4X) || \ defined(CONFIG_SOC_SERIES_STM32G4X) || \
defined(CONFIG_SOC_SERIES_STM32WLX) defined(CONFIG_SOC_SERIES_STM32WLX)
const IRQn_Type exti_irq_table[] = { static const IRQn_Type exti_irq_table[] = {
EXTI0_IRQn, EXTI1_IRQn, EXTI2_IRQn, EXTI3_IRQn, EXTI0_IRQn, EXTI1_IRQn, EXTI2_IRQn, EXTI3_IRQn,
EXTI4_IRQn, EXTI9_5_IRQn, EXTI9_5_IRQn, EXTI9_5_IRQn, EXTI4_IRQn, EXTI9_5_IRQn, EXTI9_5_IRQn, EXTI9_5_IRQn,
EXTI9_5_IRQn, EXTI9_5_IRQn, EXTI15_10_IRQn, EXTI15_10_IRQn, EXTI9_5_IRQn, EXTI9_5_IRQn, EXTI15_10_IRQn, EXTI15_10_IRQn,
EXTI15_10_IRQn, EXTI15_10_IRQn, EXTI15_10_IRQn, EXTI15_10_IRQn EXTI15_10_IRQn, EXTI15_10_IRQn, EXTI15_10_IRQn, EXTI15_10_IRQn
}; };
#elif defined(CONFIG_SOC_SERIES_STM32F3X) #elif defined(CONFIG_SOC_SERIES_STM32F3X)
const IRQn_Type exti_irq_table[] = { static const IRQn_Type exti_irq_table[] = {
EXTI0_IRQn, EXTI1_IRQn, EXTI2_TSC_IRQn, EXTI3_IRQn, EXTI0_IRQn, EXTI1_IRQn, EXTI2_TSC_IRQn, EXTI3_IRQn,
EXTI4_IRQn, EXTI9_5_IRQn, EXTI9_5_IRQn, EXTI9_5_IRQn, EXTI4_IRQn, EXTI9_5_IRQn, EXTI9_5_IRQn, EXTI9_5_IRQn,
EXTI9_5_IRQn, EXTI9_5_IRQn, EXTI15_10_IRQn, EXTI15_10_IRQn, EXTI9_5_IRQn, EXTI9_5_IRQn, EXTI15_10_IRQn, EXTI15_10_IRQn,
EXTI15_10_IRQn, EXTI15_10_IRQn, EXTI15_10_IRQn, EXTI15_10_IRQn EXTI15_10_IRQn, EXTI15_10_IRQn, EXTI15_10_IRQn, EXTI15_10_IRQn
}; };
#elif defined(CONFIG_SOC_STM32F410RX) /* STM32F410RX has no OTG_FS_WKUP_IRQn */ #elif defined(CONFIG_SOC_STM32F410RX) /* STM32F410RX has no OTG_FS_WKUP_IRQn */
const IRQn_Type exti_irq_table[] = { static const IRQn_Type exti_irq_table[] = {
EXTI0_IRQn, EXTI1_IRQn, EXTI2_IRQn, EXTI3_IRQn, EXTI0_IRQn, EXTI1_IRQn, EXTI2_IRQn, EXTI3_IRQn,
EXTI4_IRQn, EXTI9_5_IRQn, EXTI9_5_IRQn, EXTI9_5_IRQn, EXTI4_IRQn, EXTI9_5_IRQn, EXTI9_5_IRQn, EXTI9_5_IRQn,
EXTI9_5_IRQn, EXTI9_5_IRQn, EXTI15_10_IRQn, EXTI15_10_IRQn, EXTI9_5_IRQn, EXTI9_5_IRQn, EXTI15_10_IRQn, EXTI15_10_IRQn,
@ -68,7 +68,7 @@ const IRQn_Type exti_irq_table[] = {
}; };
#elif defined(CONFIG_SOC_SERIES_STM32F2X) || \ #elif defined(CONFIG_SOC_SERIES_STM32F2X) || \
defined(CONFIG_SOC_SERIES_STM32F4X) defined(CONFIG_SOC_SERIES_STM32F4X)
const IRQn_Type exti_irq_table[] = { static const IRQn_Type exti_irq_table[] = {
EXTI0_IRQn, EXTI1_IRQn, EXTI2_IRQn, EXTI3_IRQn, EXTI0_IRQn, EXTI1_IRQn, EXTI2_IRQn, EXTI3_IRQn,
EXTI4_IRQn, EXTI9_5_IRQn, EXTI9_5_IRQn, EXTI9_5_IRQn, EXTI4_IRQn, EXTI9_5_IRQn, EXTI9_5_IRQn, EXTI9_5_IRQn,
EXTI9_5_IRQn, EXTI9_5_IRQn, EXTI15_10_IRQn, EXTI15_10_IRQn, EXTI9_5_IRQn, EXTI9_5_IRQn, EXTI15_10_IRQn, EXTI15_10_IRQn,
@ -77,7 +77,7 @@ const IRQn_Type exti_irq_table[] = {
0xFF, TAMP_STAMP_IRQn, RTC_WKUP_IRQn 0xFF, TAMP_STAMP_IRQn, RTC_WKUP_IRQn
}; };
#elif defined(CONFIG_SOC_SERIES_STM32F7X) #elif defined(CONFIG_SOC_SERIES_STM32F7X)
const IRQn_Type exti_irq_table[] = { static const IRQn_Type exti_irq_table[] = {
EXTI0_IRQn, EXTI1_IRQn, EXTI2_IRQn, EXTI3_IRQn, EXTI0_IRQn, EXTI1_IRQn, EXTI2_IRQn, EXTI3_IRQn,
EXTI4_IRQn, EXTI9_5_IRQn, EXTI9_5_IRQn, EXTI9_5_IRQn, EXTI4_IRQn, EXTI9_5_IRQn, EXTI9_5_IRQn, EXTI9_5_IRQn,
EXTI9_5_IRQn, EXTI9_5_IRQn, EXTI15_10_IRQn, EXTI15_10_IRQn, EXTI9_5_IRQn, EXTI9_5_IRQn, EXTI15_10_IRQn, EXTI15_10_IRQn,
@ -88,7 +88,7 @@ const IRQn_Type exti_irq_table[] = {
#elif defined(CONFIG_SOC_SERIES_STM32MP1X) || \ #elif defined(CONFIG_SOC_SERIES_STM32MP1X) || \
defined(CONFIG_SOC_SERIES_STM32L5X) || \ defined(CONFIG_SOC_SERIES_STM32L5X) || \
defined(CONFIG_SOC_SERIES_STM32U5X) defined(CONFIG_SOC_SERIES_STM32U5X)
const IRQn_Type exti_irq_table[] = { static const IRQn_Type exti_irq_table[] = {
EXTI0_IRQn, EXTI1_IRQn, EXTI2_IRQn, EXTI3_IRQn, EXTI0_IRQn, EXTI1_IRQn, EXTI2_IRQn, EXTI3_IRQn,
EXTI4_IRQn, EXTI5_IRQn, EXTI6_IRQn, EXTI7_IRQn, EXTI4_IRQn, EXTI5_IRQn, EXTI6_IRQn, EXTI7_IRQn,
EXTI8_IRQn, EXTI9_IRQn, EXTI10_IRQn, EXTI11_IRQn, EXTI8_IRQn, EXTI9_IRQn, EXTI10_IRQn, EXTI11_IRQn,