soc: arm: atmel: Introduce sam4l SoC
Introduce SAM4L SoC initial files. Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
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Gerson Fernando Budke
Maureen Helm
parent
18e608ee55
commit
ab31a2e543
13 changed files with 1061 additions and 22 deletions
304
soc/arm/atmel_sam/sam4l/soc.c
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304
soc/arm/atmel_sam/sam4l/soc.c
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/*
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* Copyright (c) 2020 Gerson Fernando Budke <nandojve@gmail.com>
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Atmel SAM4L MCU series initialization code
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*
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* This module provides routines to initialize and support board-level hardware
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* for the Atmel SAM4L series processor.
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*/
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#include <device.h>
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#include <init.h>
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#include <soc.h>
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#include <arch/cpu.h>
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/** Watchdog control register first write keys */
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#define WDT_FIRST_KEY 0x55ul
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/** Watchdog control register second write keys */
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#define WDT_SECOND_KEY 0xAAul
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/**
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* @brief Calculate \f$ \left\lceil \frac{a}{b} \right\rceil \f$ using
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* integer arithmetic.
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*
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* @param a An integer
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* @param b Another integer
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*
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* @return (\a a / \a b) rounded up to the nearest integer.
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*/
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#define div_ceil(a, b) (((a) + (b) - 1) / (b))
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/**
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* @brief Sets the WatchDog Timer Control register to the \a ctrl value thanks
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* to the WatchDog Timer key.
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*
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* @param ctrl Value to set the WatchDog Timer Control register to.
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*/
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static ALWAYS_INLINE void wdt_set_ctrl(uint32_t ctrl)
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{
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volatile uint32_t dly;
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/** Calculate delay for internal synchronization
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* see 45.1.3 WDT errata
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*/
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dly = div_ceil(48000000 * 2, 115000);
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dly >>= 3; /* ~8 cycles for one while loop */
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while (dly--) {
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;
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};
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WDT->CTRL = ctrl | WDT_CTRL_KEY(WDT_FIRST_KEY);
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WDT->CTRL = ctrl | WDT_CTRL_KEY(WDT_SECOND_KEY);
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}
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#define XTAL_FREQ 12000000
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#define NR_PLLS 1
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#define PLL_MAX_STARTUP_CYCLES (SCIF_PLL_PLLCOUNT_Msk >> SCIF_PLL_PLLCOUNT_Pos)
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/**
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* Fcpu = 48MHz
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* Fpll = (Fclk * PLL_mul) / PLL_div
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*/
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#define PLL0_MUL (192000000 / XTAL_FREQ)
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#define PLL0_DIV 4
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static inline bool pll_is_locked(uint32_t pll_id)
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{
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return !!(SCIF->PCLKSR & (1U << (6 + pll_id)));
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}
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static inline bool osc_is_ready(uint8_t id)
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{
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switch (id) {
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case OSC_ID_OSC0:
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return !!(SCIF->PCLKSR & SCIF_PCLKSR_OSC0RDY);
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case OSC_ID_OSC32:
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return !!(BSCIF->PCLKSR & BSCIF_PCLKSR_OSC32RDY);
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case OSC_ID_RC32K:
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return !!(BSCIF->RC32KCR & (BSCIF_RC32KCR_EN));
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case OSC_ID_RC80M:
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return !!(SCIF->RC80MCR & (SCIF_RC80MCR_EN));
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case OSC_ID_RCFAST:
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return !!(SCIF->RCFASTCFG & (SCIF_RCFASTCFG_EN));
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case OSC_ID_RC1M:
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return !!(BSCIF->RC1MCR & (BSCIF_RC1MCR_CLKOE));
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case OSC_ID_RCSYS:
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/* RCSYS is always ready */
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return true;
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default:
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/* unhandled_case(id); */
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return false;
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}
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}
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/**
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* The PLL options #PLL_OPT_VCO_RANGE_HIGH and #PLL_OPT_OUTPUT_DIV will
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* be set automatically based on the calculated target frequency.
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*/
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static inline uint32_t pll_config_init(uint32_t divide, uint32_t mul)
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{
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#define SCIF0_PLL_VCO_RANGE1_MAX_FREQ 240000000
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#define SCIF_PLL0_VCO_RANGE1_MIN_FREQ 160000000
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#define SCIF_PLL0_VCO_RANGE0_MAX_FREQ 180000000
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#define SCIF_PLL0_VCO_RANGE0_MIN_FREQ 80000000
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/* VCO frequency range is 160-240 MHz (80-180 MHz if unset) */
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#define PLL_OPT_VCO_RANGE_HIGH 0
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/* Divide output frequency by two */
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#define PLL_OPT_OUTPUT_DIV 1
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/* The threshold above which to set the #PLL_OPT_VCO_RANGE_HIGH option */
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#define PLL_VCO_LOW_THRESHOLD ((SCIF_PLL0_VCO_RANGE1_MIN_FREQ \
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+ SCIF_PLL0_VCO_RANGE0_MAX_FREQ) / 2)
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#define PLL_MIN_HZ 40000000
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#define PLL_MAX_HZ 240000000
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#define MUL_MIN 2
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#define MUL_MAX 16
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#define DIV_MIN 0
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#define DIV_MAX 15
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uint32_t pll_value;
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uint32_t vco_hz;
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/* Calculate internal VCO frequency */
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vco_hz = XTAL_FREQ * mul;
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vco_hz /= divide;
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pll_value = 0;
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/* Bring the internal VCO frequency up to the minimum value */
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if ((vco_hz < PLL_MIN_HZ * 2) && (mul <= 8)) {
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mul *= 2;
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vco_hz *= 2;
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pll_value |= (1U << (SCIF_PLL_PLLOPT_Pos +
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PLL_OPT_OUTPUT_DIV));
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}
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/* Set VCO frequency range according to calculated value */
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if (vco_hz >= PLL_VCO_LOW_THRESHOLD) {
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pll_value |= 1U << (SCIF_PLL_PLLOPT_Pos +
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PLL_OPT_VCO_RANGE_HIGH);
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}
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pll_value |= ((mul - 1) << SCIF_PLL_PLLMUL_Pos) |
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(divide << SCIF_PLL_PLLDIV_Pos) |
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(PLL_MAX_STARTUP_CYCLES << SCIF_PLL_PLLCOUNT_Pos);
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return pll_value;
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}
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static inline void flashcalw_set_wait_state(uint32_t wait_state)
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{
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HFLASHC->FCR = (HFLASHC->FCR & ~FLASHCALW_FCR_FWS) |
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(wait_state ?
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FLASHCALW_FCR_FWS_1 :
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FLASHCALW_FCR_FWS_0);
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}
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static inline bool flashcalw_is_ready(void)
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{
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return ((HFLASHC->FSR & FLASHCALW_FSR_FRDY) != 0);
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}
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static inline void flashcalw_issue_command(uint32_t command, int page_number)
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{
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uint32_t time;
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flashcalw_is_ready();
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time = HFLASHC->FCMD;
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/* Clear the command bitfield. */
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time &= ~FLASHCALW_FCMD_CMD_Msk;
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if (page_number >= 0) {
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time = (FLASHCALW_FCMD_KEY_KEY |
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FLASHCALW_FCMD_PAGEN(page_number) | command);
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} else {
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time |= (FLASHCALW_FCMD_KEY_KEY | command);
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}
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HFLASHC->FCMD = time;
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flashcalw_is_ready();
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}
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/**
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* @brief Setup various clock on SoC at boot time.
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*
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* Setup the SoC clocks according to section 28.12 in datasheet.
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*
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* Setup Slow, Main, PLLA, Processor and Master clocks during the device boot.
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* It is assumed that the relevant registers are at their reset value.
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*/
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static ALWAYS_INLINE void clock_init(void)
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{
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/* Disable PicoCache and Enable HRAMC1 as extended RAM */
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soc_pmc_peripheral_enable(
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PM_CLOCK_MASK(PM_CLK_GRP_HSB, SYSCLK_HRAMC1_DATA));
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soc_pmc_peripheral_enable(
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PM_CLOCK_MASK(PM_CLK_GRP_PBB, SYSCLK_HRAMC1_REGS));
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HCACHE->CTRL = HCACHE_CTRL_CEN_NO;
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while (HCACHE->SR & HCACHE_SR_CSTS_EN) {
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;
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};
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/* Enable PLL */
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if (!pll_is_locked(0)) {
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/* This assumes external 12MHz Crystal */
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SCIF->UNLOCK = SCIF_UNLOCK_KEY(0xAAu) |
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SCIF_UNLOCK_ADDR((uint32_t)&SCIF->OSCCTRL0 -
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(uint32_t)SCIF);
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SCIF->OSCCTRL0 = SCIF_OSCCTRL0_STARTUP(2) |
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SCIF_OSCCTRL0_GAIN(3) |
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SCIF_OSCCTRL0_MODE |
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SCIF_OSCCTRL0_OSCEN;
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while (!osc_is_ready(OSC_ID_OSC0)) {
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;
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};
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uint32_t pll_config = pll_config_init(PLL0_DIV,
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PLL0_MUL);
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SCIF->UNLOCK = SCIF_UNLOCK_KEY(0xAAu) |
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SCIF_UNLOCK_ADDR((uint32_t)&SCIF->PLL[0] -
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(uint32_t)SCIF);
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SCIF->PLL[0] = pll_config | SCIF_PLL_PLLEN;
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while (!pll_is_locked(0)) {
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;
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};
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}
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/** Set a flash wait state depending on the new cpu frequency.
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*/
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flashcalw_set_wait_state(1);
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flashcalw_issue_command(FLASHCALW_FCMD_CMD_HSEN, -1);
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/** Set Clock CPU/BUS dividers
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*/
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PM->UNLOCK = PM_UNLOCK_KEY(0xAAu) |
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PM_UNLOCK_ADDR((uint32_t)&PM->CPUSEL - (uint32_t)PM);
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PM->CPUSEL = PM_CPUSEL_CPUSEL(0);
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PM->UNLOCK = PM_UNLOCK_KEY(0xAAu) |
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PM_UNLOCK_ADDR((uint32_t)&PM->PBASEL - (uint32_t)PM);
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PM->PBASEL = PM_PBASEL_PBSEL(0);
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PM->UNLOCK = PM_UNLOCK_KEY(0xAAu) |
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PM_UNLOCK_ADDR((uint32_t)&PM->PBBSEL - (uint32_t)PM);
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PM->PBBSEL = PM_PBBSEL_PBSEL(0);
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PM->UNLOCK = PM_UNLOCK_KEY(0xAAu) |
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PM_UNLOCK_ADDR((uint32_t)&PM->PBCSEL - (uint32_t)PM);
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PM->PBCSEL = PM_PBCSEL_PBSEL(0);
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PM->UNLOCK = PM_UNLOCK_KEY(0xAAu) |
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PM_UNLOCK_ADDR((uint32_t)&PM->PBDSEL - (uint32_t)PM);
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PM->PBDSEL = PM_PBDSEL_PBSEL(0);
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/** Set PLL0 as source clock
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*/
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PM->UNLOCK = PM_UNLOCK_KEY(0xAAu) |
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PM_UNLOCK_ADDR((uint32_t)&PM->MCCTRL - (uint32_t)PM);
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PM->MCCTRL = OSC_SRC_PLL0;
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}
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/**
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* @brief Perform basic hardware initialization at boot.
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*
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* This needs to be run from the very beginning.
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* So the init priority has to be 0 (zero).
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*
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* @return 0
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*/
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static int atmel_sam4l_init(const struct device *arg)
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{
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uint32_t key;
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ARG_UNUSED(arg);
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key = irq_lock();
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#if defined(CONFIG_WDT_DISABLE_AT_BOOT)
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wdt_set_ctrl(WDT->CTRL & ~WDT_CTRL_EN);
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while (WDT->CTRL & WDT_CTRL_EN) {
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;
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};
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#endif
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/* Setup system clocks. */
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clock_init();
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/*
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* Install default handler that simply resets the CPU
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* if configured in the kernel, NOP otherwise.
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*/
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NMI_INIT();
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irq_unlock(key);
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return 0;
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}
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SYS_INIT(atmel_sam4l_init, PRE_KERNEL_1, 0);
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