drivers: timer: provide timer irq to tests

As with previous commit, make the timer irq a simple integer variable
exported by the timer driver for the benefit of this one test
(tests/kernel/context).

Signed-off-by: Anas Nashif <anas.nashif@intel.com>

drivers/timer/altera_avalon_timer_hal.c

@@ -24,6 +24,10 @@ static uint32_t accumulated_cycle_count;
 
 static int32_t _sys_idle_elapsed_ticks = 1;
 
+#if defined(CONFIG_TEST)
+const int32_t z_sys_timer_irq_for_test = TIMER_0_IRQ;
+#endif
+
 static void wrapped_announce(int32_t ticks)
 {
 	driver_uptime += ticks;

drivers/timer/apic_timer.c

@@ -48,6 +48,9 @@ BUILD_ASSERT(!IS_ENABLED(CONFIG_SMP), "APIC timer doesn't support SMP");
 #define LVT_MODE_MASK		0x00060000	/* timer mode bits */
 #define LVT_MODE		0x00000000	/* one-shot */
 
+#if defined(CONFIG_TEST)
+const int32_t z_sys_timer_irq_for_test = CONFIG_APIC_TIMER_IRQ;
+#endif
 /*
  * CYCLES_PER_TICK must always be at least '2', otherwise MAX_TICKS
  * will overflow int32_t, which is how 'ticks' are currently represented.

drivers/timer/arcv2_timer0.c

@@ -54,6 +54,9 @@
 
 #define SMP_TIMER_DRIVER (CONFIG_SMP && CONFIG_MP_NUM_CPUS > 1)
 
+#if defined(CONFIG_TEST)
+const int32_t z_sys_timer_irq_for_test = IRQ_TIMER0;
+#endif
 static struct k_spinlock lock;
 
 

drivers/timer/arm_arch_timer.c

@@ -17,6 +17,9 @@
 
 static struct k_spinlock lock;
 static uint64_t last_cycle;
+#if defined(CONFIG_TEST)
+const int32_t z_sys_timer_irq_for_test = ARM_ARCH_TIMER_IRQ;
+#endif
 
 static void arm_arch_timer_compare_isr(const void *arg)
 {

drivers/timer/cavs_timer.c

@@ -41,7 +41,9 @@ BUILD_ASSERT(COMPARATOR_IDX >= 0 && COMPARATOR_IDX <= 1);
 static struct k_spinlock lock;
 static uint64_t last_count;
 
+#if defined(CONFIG_TEST)
 const int32_t z_sys_timer_irq_for_test = TIMER_IRQ; /* See tests/kernel/context */
+#endif
 
 static void set_compare(uint64_t time)
 {

drivers/timer/esp32c3_sys_timer.c

@@ -25,6 +25,10 @@
 #define MAX_TICKS ((MAX_CYC - CYC_PER_TICK) / CYC_PER_TICK)
 #define MIN_DELAY 1000
 
+#if defined(CONFIG_TEST)
+const int32_t z_sys_timer_irq_for_test = DT_IRQN(DT_NODELABEL(systimer0));
+#endif
+
 #define TICKLESS IS_ENABLED(CONFIG_TICKLESS_KERNEL)
 
 static struct k_spinlock lock;

drivers/timer/hpet.c

@@ -86,6 +86,10 @@ DEVICE_MMIO_TOPLEVEL_STATIC(hpet_regs, DT_DRV_INST(0));
 #define TIMER0_COMPARATOR_LOW_REG	HPET_REG_ADDR(0x108)
 #define TIMER0_COMPARATOR_HIGH_REG	HPET_REG_ADDR(0x10c)
 
+#if defined(CONFIG_TEST)
+const int32_t z_sys_timer_irq_for_test = DT_IRQN(DT_INST(0, intel_hpet));
+#endif
+
 /**
  * @brief Return the value of the main counter.
  *

drivers/timer/ite_it8xxx2_timer.c

@@ -37,6 +37,10 @@ BUILD_ASSERT(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC == 32768,
 /* Busy wait high timer max count is 71.58min (base on clock source 1MHz) */
 #define BUSY_WAIT_TIMER_H_MAX_CNT 0xFFFFFFFFUL
 
+#if defined(CONFIG_TEST)
+const int32_t z_sys_timer_irq_for_test = DT_IRQ_BY_IDX(DT_NODELABEL(timer), 5, irq);
+#endif
+
 #ifdef CONFIG_SOC_IT8XXX2_PLL_FLASH_48M
 /*
  * One shot timer configurations

drivers/timer/litex_timer.c

@@ -29,6 +29,9 @@
 #define TIMER_DISABLE		0x0
 #define TIMER_ENABLE		0x1
 #define TIMER_UPTIME_LATCH	0x1
+#if defined(CONFIG_TEST)
+const int32_t z_sys_timer_irq_for_test = TIMER_IRQ;
+#endif
 
 static void litex_timer_irq_handler(const void *device)
 {

drivers/timer/rcar_cmt_timer.c

@@ -21,6 +21,9 @@
 #define CYCLES_PER_SEC         TIMER_CLOCK_FREQUENCY
 #define CYCLES_PER_TICK        (CYCLES_PER_SEC / CONFIG_SYS_CLOCK_TICKS_PER_SEC)
 
+#if defined(CONFIG_TEST)
+const int32_t z_sys_timer_irq_for_test = DT_IRQN(DT_INST(0, renesas_rcar_cmt));
+#endif
 static struct rcar_cpg_clk mod_clk = {
 	.module = DT_INST_CLOCKS_CELL(0, module),
 	.domain = DT_INST_CLOCKS_CELL(0, domain),

drivers/timer/riscv_machine_timer.c

@@ -20,6 +20,9 @@
 
 static struct k_spinlock lock;
 static uint64_t last_count;
+#if defined(CONFIG_TEST)
+const int32_t z_sys_timer_irq_for_test = RISCV_MACHINE_TIMER_IRQ;
+#endif
 
 static uint64_t get_hart_mtimecmp(void)
 {

drivers/timer/rv32m1_lptmr_timer.c

@@ -24,6 +24,9 @@
 
 #define CYCLES_PER_SEC  sys_clock_hw_cycles_per_sec()
 #define CYCLES_PER_TICK (CYCLES_PER_SEC / CONFIG_SYS_CLOCK_TICKS_PER_SEC)
+#if defined(CONFIG_TEST)
+const int32_t z_sys_timer_irq_for_test = DT_IRQN(DT_ALIAS(system_lptmr));
+#endif
 
 /*
  * As a simplifying assumption, we only support a clock ticking at the

drivers/timer/xlnx_psttc_timer.c

@@ -22,6 +22,9 @@
 #define CYCLES_PER_SEC		TIMER_CLOCK_FREQUECY
 #define CYCLES_PER_TICK		(CYCLES_PER_SEC / TICKS_PER_SEC)
 
+#if defined(CONFIG_TEST)
+const int32_t z_sys_timer_irq_for_test = DT_IRQN(DT_INST(0, xlnx_ttcps));
+#endif
 /*
  * CYCLES_NEXT_MIN must be large enough to ensure that the timer does not miss
  * interrupts.  This value was conservatively set using the trial and error

drivers/timer/xtensa_sys_timer.c

@@ -20,6 +20,11 @@
 static struct k_spinlock lock;
 static unsigned int last_count;
 
+#if defined(CONFIG_TEST)
+const int32_t z_sys_timer_irq_for_test = UTIL_CAT(XCHAL_TIMER,
+					 UTIL_CAT(CONFIG_XTENSA_TIMER_ID, _INTERRUPT));
+#endif
+
 static void set_ccompare(uint32_t val)
 {
 	__asm__ volatile ("wsr.CCOMPARE" STRINGIFY(CONFIG_XTENSA_TIMER_ID) " %0"

tests/kernel/context/src/main.c

@@ -45,35 +45,9 @@
  * Get the timer type dependent IRQ number. If timer type
  * is not defined in platform, generate an error
  */
-#if defined(CONFIG_HPET_TIMER)
-#define TICK_IRQ DT_IRQN(DT_INST(0, intel_hpet))
-#elif defined(CONFIG_ARM_ARCH_TIMER)
-#define TICK_IRQ ARM_ARCH_TIMER_IRQ
-#elif defined(CONFIG_APIC_TIMER)
-#define TICK_IRQ CONFIG_APIC_TIMER_IRQ
-#elif defined(CONFIG_APIC_TSC_DEADLINE_TIMER)
+
+#if defined(CONFIG_APIC_TSC_DEADLINE_TIMER)
 #define TICK_IRQ z_loapic_irq_base() /* first LVT interrupt */
-#elif defined(CONFIG_XTENSA_TIMER)
-#define TICK_IRQ UTIL_CAT(XCHAL_TIMER,		\
-			  UTIL_CAT(CONFIG_XTENSA_TIMER_ID, _INTERRUPT))
-#elif defined(CONFIG_ALTERA_AVALON_TIMER)
-#define TICK_IRQ TIMER_0_IRQ
-#elif defined(CONFIG_ARCV2_TIMER)
-#define TICK_IRQ IRQ_TIMER0
-#elif defined(CONFIG_RISCV_MACHINE_TIMER)
-#define TICK_IRQ RISCV_MACHINE_TIMER_IRQ
-#elif defined(CONFIG_ITE_IT8XXX2_TIMER)
-#define TICK_IRQ DT_IRQ_BY_IDX(DT_NODELABEL(timer), 5, irq)
-#elif defined(CONFIG_LITEX_TIMER)
-#define TICK_IRQ DT_IRQN(DT_NODELABEL(timer0))
-#elif defined(CONFIG_RV32M1_LPTMR_TIMER)
-#define TICK_IRQ DT_IRQN(DT_ALIAS(system_lptmr))
-#elif defined(CONFIG_XLNX_PSTTC_TIMER)
-#define TICK_IRQ DT_IRQN(DT_INST(0, xlnx_ttcps))
-#elif defined(CONFIG_RCAR_CMT_TIMER)
-#define TICK_IRQ DT_IRQN(DT_INST(0, renesas_rcar_cmt))
-#elif defined(CONFIG_ESP32C3_SYS_TIMER)
-#define TICK_IRQ DT_IRQN(DT_NODELABEL(systimer0))
 #elif defined(CONFIG_CPU_CORTEX_M)
 /*
  * The Cortex-M use the SYSTICK exception for the system timer, which is
@@ -92,10 +66,7 @@
 #endif /* defined(CONFIG_ARCH_POSIX) */
 #else
 
-/* Ooooooph.  All that is a mess.  Here's the new API to be portably
- * supported by timer drivers:
- */
-extern int32_t z_sys_timer_irq_for_test;
+extern const int32_t z_sys_timer_irq_for_test;
 #define TICK_IRQ (z_sys_timer_irq_for_test)
 
 #endif