quark_se_ss: power_mgmt: Remove redundant int trigger setting
Zephyr is always setting irqs to be level triggered as required by the core. It is unnecessary to set it to level again while entering sleep states. Change-Id: I10f919d619af2e1ab05dc85a67766929b6ae9402 Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
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@ -31,36 +31,12 @@
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#define ARC_SS1 (SLEEP_MODE_CORE_OFF | ENABLE_INTERRUPTS)
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#define ARC_SS2 (SLEEP_MODE_CORE_TIMERS_RTC_OFF | ENABLE_INTERRUPTS)
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#if (CONFIG_RTC)
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static unsigned int rtc_trigger;
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#endif
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#if (CONFIG_COUNTER)
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static unsigned int aonpt_trigger;
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#endif
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/* QMSI does not set the interrupt enable bit in the sleep operand.
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* For the time being, implement this in Zephyr.
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* This will be removed once QMSI is fixed.
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*/
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static void enter_arc_state(int mode)
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{
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/* The sensor cannot be woken up with an edge triggered
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* interrupt from the RTC and the AON Counter.
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* Switch to Level triggered interrupts and restore
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* the setting when waking up.
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*/
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#if (CONFIG_RTC)
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rtc_trigger = _arc_v2_irq_unit_trigger_get(QM_IRQ_RTC_0_INT_VECTOR);
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_arc_v2_irq_unit_trigger_set(QM_IRQ_RTC_0_INT_VECTOR,
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_ARC_V2_INT_LEVEL);
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#endif
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#if (CONFIG_COUNTER)
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aonpt_trigger = _arc_v2_irq_unit_trigger_get(QM_IRQ_AONPT_0_INT_VECTOR);
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_arc_v2_irq_unit_trigger_set(QM_IRQ_AONPT_0_INT_VECTOR,
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_ARC_V2_INT_LEVEL);
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#endif
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/* Enter SSx */
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__asm__ volatile("sleep %0"
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: /* No output operands. */
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@ -90,31 +66,14 @@ void _sys_soc_set_power_state(enum power_states state)
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}
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}
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static void restore_interrupt_trigger(void)
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{
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/* Restore the RTC and AONC interrupt trigger after wake up */
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#if (CONFIG_RTC)
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_arc_v2_irq_unit_trigger_set(QM_IRQ_RTC_0_INT_VECTOR, rtc_trigger);
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#endif
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#if (CONFIG_COUNTER)
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_arc_v2_irq_unit_trigger_set(QM_IRQ_AONPT_0_INT_VECTOR, aonpt_trigger);
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#endif
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}
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void _sys_soc_power_state_post_ops(enum power_states state)
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{
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uint32_t limit;
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switch (state) {
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case SYS_POWER_STATE_CPU_LPS_2:
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/* Restore interrupts to their previous trigger type. */
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restore_interrupt_trigger();
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break;
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case SYS_POWER_STATE_CPU_LPS:
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ss_power_soc_lpss_disable();
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case SYS_POWER_STATE_CPU_LPS_1:
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restore_interrupt_trigger();
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/* Expire the timer as it is disabled in SS2. */
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limit = _arc_v2_aux_reg_read(_ARC_V2_TMR0_LIMIT);
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_arc_v2_aux_reg_write(_ARC_V2_TMR0_COUNT, limit - 1);
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