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dma: dts: Rename of the dma_buf_alignment to dma-buf-addr-alignment

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Renamed the dma-buf-alignment field to a more explicit
and descriptive name dma-buf-addr-alignment.

Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
This commit is contained in:
Adrian Warecki 2022-11-18 13:03:14 +01:00 • committed by Anas Nashif
commit aac03280ec
12 changed files with 23 additions and 23 deletions
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4
dts/bindings/dma/dma-controller.yaml
View file

@ -28,6 +28,6 @@ properties:
type: int type: int
description: Number of DMA request signals supported by the controller. description: Number of DMA request signals supported by the controller.
dma-buf-alignment: dma-buf-addr-alignment:
type: int type: int
description: Memory alignment requirement for DMA buffers used by the controller. description: Memory address alignment requirement for DMA buffers used by the controller.

2
dts/bindings/dma/intel,adsp-hda.yaml
View file

@ -15,5 +15,5 @@ properties:
"#dma-cells": "#dma-cells":
const: 1 const: 1
"dma-buf-alignment": "dma-buf-addr-alignment":
required: true required: true

8
dts/xtensa/intel/intel_adsp_ace15_mtpm.dtsi
View file

@ -342,7 +342,7 @@
#dma-cells = <1>; #dma-cells = <1>;
reg = <0x00072400 0x20>; reg = <0x00072400 0x20>;
dma-channels = <9>; dma-channels = <9>;
dma-buf-alignment = <128>; dma-buf-addr-alignment = <128>;
status = "okay"; status = "okay";
}; };
@ -351,7 +351,7 @@
#dma-cells = <1>; #dma-cells = <1>;
reg = <0x00072600 0x20>; reg = <0x00072600 0x20>;
dma-channels = <10>; dma-channels = <10>;
dma-buf-alignment = <128>; dma-buf-addr-alignment = <128>;
status = "okay"; status = "okay";
}; };
@ -360,7 +360,7 @@
#dma-cells = <1>; #dma-cells = <1>;
reg = <0x00072800 0x40>; reg = <0x00072800 0x40>;
dma-channels = <9>; dma-channels = <9>;
dma-buf-alignment = <128>; dma-buf-addr-alignment = <128>;
status = "okay"; status = "okay";
}; };
@ -369,7 +369,7 @@
#dma-cells = <1>; #dma-cells = <1>;
reg = <0x00072c00 0x40>; reg = <0x00072c00 0x40>;
dma-channels = <10>; dma-channels = <10>;
dma-buf-alignment = <128>; dma-buf-addr-alignment = <128>;
status = "okay"; status = "okay";
}; };

8
dts/xtensa/intel/intel_adsp_cavs.dtsi
View file

@ -35,7 +35,7 @@
#dma-cells = <1>; #dma-cells = <1>;
reg = <0x00072400 0x20>; reg = <0x00072400 0x20>;
dma-channels = <4>; dma-channels = <4>;
dma-buf-alignment = <128>; dma-buf-addr-alignment = <128>;
status = "okay"; status = "okay";
}; };
@ -45,7 +45,7 @@
#dma-cells = <1>; #dma-cells = <1>;
reg = <0x00072600 0x20>; reg = <0x00072600 0x20>;
dma-channels = <4>; dma-channels = <4>;
dma-buf-alignment = <128>; dma-buf-addr-alignment = <128>;
status = "okay"; status = "okay";
}; };
@ -55,7 +55,7 @@
#dma-cells = <1>; #dma-cells = <1>;
reg = <0x00072800 0x40>; reg = <0x00072800 0x40>;
dma-channels = <9>; dma-channels = <9>;
dma-buf-alignment = <128>; dma-buf-addr-alignment = <128>;
status = "okay"; status = "okay";
}; };
@ -65,7 +65,7 @@
#dma-cells = <1>; #dma-cells = <1>;
reg = <0x00072c00 0x40>; reg = <0x00072c00 0x40>;
dma-channels = <7>; dma-channels = <7>;
dma-buf-alignment = <128>; dma-buf-addr-alignment = <128>;
status = "okay"; status = "okay";
}; };

8
dts/xtensa/intel/intel_adsp_cavs15.dtsi
View file

@ -190,7 +190,7 @@
#dma-cells = <1>; #dma-cells = <1>;
reg = <0x00002400 0x20>; reg = <0x00002400 0x20>;
dma-channels = <2>; dma-channels = <2>;
dma-buf-alignment = <128>; dma-buf-addr-alignment = <128>;
status = "okay"; status = "okay";
}; };
@ -200,7 +200,7 @@
#dma-cells = <1>; #dma-cells = <1>;
reg = <0x00002600 0x20>; reg = <0x00002600 0x20>;
dma-channels = <2>; dma-channels = <2>;
dma-buf-alignment = <128>; dma-buf-addr-alignment = <128>;
status = "okay"; status = "okay";
}; };
@ -210,7 +210,7 @@
#dma-cells = <1>; #dma-cells = <1>;
reg = <0x00002800 0x40>; reg = <0x00002800 0x40>;
dma-channels = <6>; dma-channels = <6>;
dma-buf-alignment = <128>; dma-buf-addr-alignment = <128>;
status = "okay"; status = "okay";
}; };
@ -220,7 +220,7 @@
#dma-cells = <1>; #dma-cells = <1>;
reg = <0x00002c00 0x40>; reg = <0x00002c00 0x40>;
dma-channels = <7>; dma-channels = <7>;
dma-buf-alignment = <128>; dma-buf-addr-alignment = <128>;
status = "okay"; status = "okay";
}; };

4
include/zephyr/drivers/dma.h
View file

@ -642,7 +642,7 @@ static inline uint32_t dma_burst_index(uint32_t burst)
} }
/** /**
* Get the device tree property describing the buffer alignment * Get the device tree property describing the buffer address alignment
* *
* Useful when statically defining or allocating buffers for DMA usage where * Useful when statically defining or allocating buffers for DMA usage where
* memory alignment often matters. * memory alignment often matters.
@ -650,7 +650,7 @@ static inline uint32_t dma_burst_index(uint32_t burst)
* @param node Node identifier, e.g. DT_NODELABEL(dma_0) * @param node Node identifier, e.g. DT_NODELABEL(dma_0)
* @return alignment Memory byte alignment required for DMA buffers * @return alignment Memory byte alignment required for DMA buffers
*/ */
#define DMA_BUF_ALIGNMENT(node) DT_PROP(node, dma_buf_alignment) #define DMA_BUF_ADDR_ALIGNMENT(node) DT_PROP(node, dma_buf_addr_alignment)
/** /**
* @} * @}

2
subsys/logging/backends/log_backend_adsp_hda.c
View file

@ -22,7 +22,7 @@ static uint32_t hda_log_chan;
/* /*
* HDA requires 128 byte aligned data and 128 byte aligned transfers. * HDA requires 128 byte aligned data and 128 byte aligned transfers.
*/ */
#define ALIGNMENT DMA_BUF_ALIGNMENT(DT_NODELABEL(hda_host_in)) #define ALIGNMENT DMA_BUF_ADDR_ALIGNMENT(DT_NODELABEL(hda_host_in))
static __aligned(ALIGNMENT) uint8_t hda_log_buf[CONFIG_LOG_BACKEND_ADSP_HDA_SIZE]; static __aligned(ALIGNMENT) uint8_t hda_log_buf[CONFIG_LOG_BACKEND_ADSP_HDA_SIZE];
static volatile uint32_t hda_log_buffered; static volatile uint32_t hda_log_buffered;
static struct k_timer hda_log_timer; static struct k_timer hda_log_timer;

2
tests/boards/intel_adsp/hda/src/dma.c
View file

@ -14,7 +14,7 @@
#define TRANSFER_SIZE 256 #define TRANSFER_SIZE 256
#define TRANSFER_COUNT 8 #define TRANSFER_COUNT 8
#define ALIGNMENT DMA_BUF_ALIGNMENT(DT_NODELABEL(hda_host_in)) #define ALIGNMENT DMA_BUF_ADDR_ALIGNMENT(DT_NODELABEL(hda_host_in))
static __aligned(ALIGNMENT) uint8_t dma_buf[DMA_BUF_SIZE]; static __aligned(ALIGNMENT) uint8_t dma_buf[DMA_BUF_SIZE];
#define HDA_HOST_IN_BASE DT_PROP_BY_IDX(DT_NODELABEL(hda_host_in), reg, 0) #define HDA_HOST_IN_BASE DT_PROP_BY_IDX(DT_NODELABEL(hda_host_in), reg, 0)

2
tests/boards/intel_adsp/hda/src/smoke.c
View file

@ -20,7 +20,7 @@
#define HDA_BUF_SIZE 256 #define HDA_BUF_SIZE 256
#define TRANSFER_COUNT 8 #define TRANSFER_COUNT 8
#define ALIGNMENT DT_PROP(DT_NODELABEL(hda_host_in), dma_buf_alignment) #define ALIGNMENT DT_PROP(DT_NODELABEL(hda_host_in), dma_buf_addr_alignment)
static __aligned(ALIGNMENT) uint8_t hda_buf[HDA_BUF_SIZE]; static __aligned(ALIGNMENT) uint8_t hda_buf[HDA_BUF_SIZE];
static volatile int msg_cnt; static volatile int msg_cnt;

2
tests/drivers/adc/adc_dma/boards/frdm_k64f.overlay
View file

@ -12,7 +12,7 @@
}; };
&edma0 { &edma0 {
dma-buf-alignment = <4>; dma-buf-addr-alignment = <4>;
}; };
test_dma: &edma0 { }; test_dma: &edma0 { };

2
tests/drivers/adc/adc_dma/boards/frdm_k82f.overlay
View file

@ -12,7 +12,7 @@
}; };
&edma0 { &edma0 {
dma-buf-alignment = <4>; dma-buf-addr-alignment = <4>;
}; };
test_dma: &edma0 { }; test_dma: &edma0 { };

2
tests/drivers/adc/adc_dma/src/test_adc.c
View file

@ -38,7 +38,7 @@
#define SAMPLE_INTERVAL_US (10000U) #define SAMPLE_INTERVAL_US (10000U)
#define BUFFER_SIZE 24 #define BUFFER_SIZE 24
#define ALIGNMENT DMA_BUF_ALIGNMENT(DT_NODELABEL(test_dma)) #define ALIGNMENT DMA_BUF_ADDR_ALIGNMENT(DT_NODELABEL(test_dma))
static ZTEST_BMEM __aligned(ALIGNMENT) int16_t m_sample_buffer[BUFFER_SIZE]; static ZTEST_BMEM __aligned(ALIGNMENT) int16_t m_sample_buffer[BUFFER_SIZE];
static ZTEST_BMEM __aligned(ALIGNMENT) int16_t m_sample_buffer2[2][BUFFER_SIZE]; static ZTEST_BMEM __aligned(ALIGNMENT) int16_t m_sample_buffer2[2][BUFFER_SIZE];
static int current_buf_inx; static int current_buf_inx;