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board: nucleo_h745zi_q: Convert to dts based clock configuration

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Configure board clocks using device tree.

Bus clocks configuration part is kept common to both cores.
On core dedicated configuration we find:
- Specific sysclock freq on both cores
- Sysclk input clock selection on M7 core only (as per existing
clock_control driver behavior).

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
Erwan Gouriou 2021-04-29 14:48:04 +02:00 • committed by Carles Cufí
commit aab7fafe9d
6 changed files with 36 additions and 40 deletions
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20
boards/arm/nucleo_h745zi_q/Kconfig.defconfig
View file

@ -9,26 +9,6 @@ config BOARD
default "nucleo_h745zi_q_m7" if BOARD_NUCLEO_H745ZI_Q_M7
default "nucleo_h745zi_q_m4" if BOARD_NUCLEO_H745ZI_Q_M4
config CLOCK_STM32_D1CPRE
default 1
config CLOCK_STM32_HPRE
# HCLK: 240MHz
default 2
config CLOCK_STM32_D2PPRE1
# APBX: 120MHz
default 2
config CLOCK_STM32_D2PPRE2
default 2
config CLOCK_STM32_D1PPRE
default 2
config CLOCK_STM32_D3PPRE
default 2
config STM32H7_DUAL_CORE
default y

9
boards/arm/nucleo_h745zi_q/nucleo_h745zi_q.dtsi
View file

@ -28,3 +28,12 @@
};
};
};
&rcc {
d1cpre = <1>;
hpre = <2>;
d1ppre = <2>;
d2ppre1 = <2>;
d2ppre2 = <2>;
d3ppre = <2>;
};

4
boards/arm/nucleo_h745zi_q/nucleo_h745zi_q_m4.dts
View file

@ -30,3 +30,7 @@
current-speed = <115200>;
status = "okay";
};
&rcc {
clock-frequency = <DT_FREQ_M(240)>;
};

4
boards/arm/nucleo_h745zi_q/nucleo_h745zi_q_m4_defconfig
View file

@ -2,8 +2,6 @@
CONFIG_SOC_SERIES_STM32H7X=y
CONFIG_SOC_STM32H745XX=y
# SYS_CLOCK_M4 = SYS_CLOCK_M7 / CLOCK_STM32_HPRE
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=240000000
# Board config should be specified since there are 2 possible targets
CONFIG_BOARD_NUCLEO_H745ZI_Q_M4=y
@ -14,7 +12,7 @@ CONFIG_PINMUX=y
# Enable GPIO
CONFIG_GPIO=y
# Clock Configuration
# Enable clock
CONFIG_CLOCK_CONTROL=y
# By default SERIAL peripherals are assigned to m7

21
boards/arm/nucleo_h745zi_q/nucleo_h745zi_q_m7.dts
View file

@ -45,6 +45,27 @@
};
};
&clk_hse {
hse-bypass;
clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
status = "okay";
};
&pll {
div-m = <1>;
mul-n = <120>;
div-p = <2>;
div-q = <2>;
div-r = <2>;
clocks = <&clk_hse>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(480)>;
};
&usart3 {
pinctrl-0 = <&usart3_tx_pd8 &usart3_rx_pd9>;
current-speed = <115200>;

18
boards/arm/nucleo_h745zi_q/nucleo_h745zi_q_m7_defconfig
View file

@ -2,7 +2,6 @@
CONFIG_SOC_SERIES_STM32H7X=y
CONFIG_SOC_STM32H745XX=y
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=480000000
# Board config should be specified since there are 2 possible targets
CONFIG_BOARD_NUCLEO_H745ZI_Q_M7=y
@ -26,20 +25,5 @@ CONFIG_PINMUX=y
# Enable GPIO
CONFIG_GPIO=y
# Clock Configuration
# Enable Clock
CONFIG_CLOCK_CONTROL=y
# STLINK provides 8MHz clock input
CONFIG_CLOCK_STM32_HSE_CLOCK=8000000
CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
# Use HSE (bypass) as PLL input
CONFIG_CLOCK_STM32_PLL_SRC_HSE=y
CONFIG_CLOCK_STM32_HSE_BYPASS=y
# Produce 480MHz clock at PLL1 output
CONFIG_CLOCK_STM32_PLL_M_DIVISOR=1
CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=120
CONFIG_CLOCK_STM32_PLL_P_DIVISOR=2
CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=2
CONFIG_CLOCK_STM32_PLL_R_DIVISOR=2