sys_log: replace debug macros at Freescale K64 PWM driver
Freescale K64 PWM driver is now using new system log macros, updated the Kconfig variable to be a level rather than a bool. JIRA: ZEP-311 Change-Id: I80d01ba75e8b186ef32861b372af4e2d15dd4131 Signed-off-by: Genaro Saucedo Tejada <genaro.saucedo.tejada@intel.com>
This commit is contained in:
Genaro Saucedo Tejada
Andrew Boie
parent
eaebd1774b
commit
aaa66ee9f2
2 changed files with 66 additions and 56 deletions
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@ -31,12 +31,25 @@ menuconfig PWM_K64_FTM
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if PWM_K64_FTM
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config PWM_K64_FTM_DEBUG
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bool "Enable Debugging for pwm_ftm driver"
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config SYS_LOG_PWM_K64_FTM_LEVEL
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int
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prompt "Sets log level for pwm_ftm driver"
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depends on PWM_K64_FTM
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default n
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default 0
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help
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Enable debugging for pwm_ftm driver.
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Sets log level for pwm_ftm driver.
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Levels are:
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- 0 OFF, do not write
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- 1 ERROR, only write SYS_LOG_ERR
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- 2 WARNING, write SYS_LOG_WRN in adition to previous level
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- 3 INFO, write SYS_LOG_INF in adition to previous levels
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- 4 DEBUG, write SYS_LOG_DBG in adition to previous levels
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#### FTM0 #####
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@ -29,7 +29,7 @@
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* - CONFIG_PWM_K64_FTM_x_DEV_NAME: string representing the device name
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* - CONFIG_PWM_K64_FTM_x_PRESCALE: the clock prescaler value
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* - CONFIG_PWM_K64_FTM_x_CLOCK_SOURCE: the clock source
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* - CONFIG_PWM_K64_FTM_DEBUG: enable debug log output for the driver
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* - CONFIG_SYS_LOG_PWM_K64_FTM_LEVEL: sets log output level for the driver
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* - CONFIG_STDOUT_CONSOLE: choose debug logs using printf of printk
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*
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* The following configuration options need to be defined in
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@ -63,17 +63,8 @@
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*/
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#undef COMBINE_MODE_SUPPORT
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#ifndef CONFIG_PWM_K64_FTM_DEBUG
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#define DBG(...) do { } while ((0))
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#else /* CONFIG_PWM_K64_FTM_DEBUG */
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#if defined(CONFIG_STDOUT_CONSOLE)
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#include <stdio.h>
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#define DBG printf
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#else
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#include <misc/printk.h>
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#define DBG printk
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#endif /* CONFIG_STDOUT_CONSOLE */
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#endif /* CONFIG_PWM_K64_FTM_DEBUG */
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#define SYS_LOG_LEVEL CONFIG_SYS_LOG_PWM_K64_FTM_LEVEL
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#include <misc/sys_log.h>
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/* Maximum PWM outputs */
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#define MAX_PWM_OUT 8
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@ -96,8 +87,8 @@ static int pwm_ftm_clk_enable(uint8_t ftm_num)
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(volatile struct K20_SIM *)PERIPH_ADDR_BASE_SIM; /* sys integ. ctl */
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if (ftm_num > 3) {
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DBG("ERROR: Illegal FTM number (%d).\n"
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" Cannot enable PWM clock\n", ftm_num);
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SYS_LOG_ERR("Illegal FTM number (%d).\n Cannot enable PWM "
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"clock", ftm_num);
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return -EINVAL;
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}
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@ -135,7 +126,7 @@ static int pwm_ftm_configure(struct device *dev, int access_op,
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uint32_t reg_val;
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DBG("pwm_ftm_configure...\n");
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SYS_LOG_DBG("...");
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const struct pwm_ftm_config * const config =
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dev->config->config_info;
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@ -165,7 +156,7 @@ static int pwm_ftm_configure(struct device *dev, int access_op,
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clock_source = (config->clock_source & 0x3) << PWM_K64_FTM_SC_CLKS_SHIFT;
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if (clock_source == 0) {
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DBG("Warning: no clock source. PWM is disabled\n");
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SYS_LOG_DBG("Warning: no clock source. PWM is disabled");
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}
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@ -215,14 +206,14 @@ static int pwm_ftm_configure(struct device *dev, int access_op,
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mode_reg_val = sys_read32(PWM_K64_FTM_MODE(config->reg_base));
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mode_reg_val |= PWM_K64_FTM_MODE_FTMEN | PWM_K64_FTM_MODE_INIT;
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DBG("pwm_ftm_configure sys_write32(0x%08x, 0x%08x)..\n",
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SYS_LOG_DBG("sys_write32(0x%08x, 0x%08x)..",
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mode_reg_val, PWM_K64_FTM_MODE(config->reg_base));
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sys_write32(mode_reg_val, PWM_K64_FTM_MODE(config->reg_base));
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/* Enable enhanced synchronization */
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DBG("pwm_ftm_configure sys_write32(0x%08x, 0x%08x)..\n",
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SYS_LOG_DBG("sys_write32(0x%08x, 0x%08x)..",
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PWM_K64_FTM_SYNCONF_SYNCMODE|PWM_K64_FTM_SYNCONF_CNTINC,
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PWM_K64_FTM_SYNCONF(config->reg_base));
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@ -234,12 +225,12 @@ static int pwm_ftm_configure(struct device *dev, int access_op,
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/* Configure: PS | CLKS | up-counter | disable TOF intr */
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reg_val = prescale | clock_source;
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DBG("pwm_ftm_configure sys_write32(0x%08x, 0x%08x)..\n",
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SYS_LOG_DBG("sys_write32(0x%08x, 0x%08x)..",
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reg_val, PWM_K64_FTM_SC(config->reg_base));
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sys_write32(reg_val, PWM_K64_FTM_SC(config->reg_base));
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DBG("pwm_ftm_configure sys_write32(0x%08x, 0x%08x)..\n",
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SYS_LOG_DBG("sys_write32(0x%08x, 0x%08x)..",
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config->period, PWM_K64_FTM_MOD(config->reg_base));
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/* set MOD to max */
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@ -248,18 +239,18 @@ static int pwm_ftm_configure(struct device *dev, int access_op,
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/* set channel control to edge-aligned */
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reg_val = PWM_K64_FTM_CNSC_MSB | PWM_K64_FTM_CNSC_ELSB;
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DBG("pwm_ftm_configure sys_write32(0x%08x, 0x%08x)..\n",
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SYS_LOG_DBG("sys_write32(0x%08x, 0x%08x)..",
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reg_val, PWM_K64_FTM_CNSC(config->reg_base, channel));
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sys_write32(reg_val, PWM_K64_FTM_CNSC(config->reg_base, channel));
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DBG("pwm_ftm_configure sys_read32 4..\n");
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SYS_LOG_DBG("sys_read32 4..");
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/* set polarity high for this channel */
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polarity = sys_read32(PWM_K64_FTM_POL(config->reg_base));
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polarity &= ~(1<<channel);
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DBG("pwm_ftm_configure sys_write32(0x%08x, 0x%08x)..\n",
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SYS_LOG_DBG("sys_write32(0x%08x, 0x%08x)..",
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polarity, PWM_K64_FTM_POL(config->reg_base));
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sys_write32(polarity, PWM_K64_FTM_POL(config->reg_base));
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@ -291,7 +282,7 @@ static int pwm_ftm_set_values(struct device *dev, int access_op,
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struct pwm_ftm_drv_data * const drv_data =
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(struct pwm_ftm_drv_data * const)dev->driver_data;
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DBG("pwm_ftm_set_values (on=%d, off=%d)\n", on, off);
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SYS_LOG_DBG("(on=%d, off=%d)", on, off);
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uint32_t pwm_pair;
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uint32_t combine;
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@ -313,7 +304,7 @@ static int pwm_ftm_set_values(struct device *dev, int access_op,
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if ((on >= config->period) || (off >= config->period)) {
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/* Fully on. Set to 100% */
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DBG("pwm_ftm_set_values sys_write32(0x%08x, 0x%08x)..\n",
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SYS_LOG_DBG("sys_write32(0x%08x, 0x%08x)..",
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config->period, PWM_K64_FTM_CNV(config->reg_base, channel));
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/* CnV = pulse width */
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@ -322,7 +313,7 @@ static int pwm_ftm_set_values(struct device *dev, int access_op,
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} else if (off == 0) {
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/* Fully off. Set to 0% */
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DBG("pwm_ftm_set_values sys_write32(0x%08x, 0x%08x)..\n",
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SYS_LOG_DBG("sys_write32(0x%08x, 0x%08x)..",
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0, PWM_K64_FTM_CNV(config->reg_base, channel));
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/* CnV = 0 */
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@ -342,12 +333,14 @@ static int pwm_ftm_set_values(struct device *dev, int access_op,
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/* If phase != 0 enable combine mode */
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if (channel % 2 != 0) {
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DBG("If Phase is non-zero pwm must be 0, 2, 4, 6.\n");
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SYS_LOG_DBG("If Phase is non-zero pwm must be "
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"0, 2, 4, 6.");
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return -EINVAL;
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}
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DBG("Note: Enabling phase on pwm%d therefore "
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"pwm%d is not valid for output\n", channel, channel+1);
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SYS_LOG_DBG("Note: Enabling phase on pwm%d therefore "
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"pwm%d is not valid for output", channel,
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channel+1);
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pwm_pair = channel / 2;
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@ -355,14 +348,16 @@ static int pwm_ftm_set_values(struct device *dev, int access_op,
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switch (pwm_pair) {
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case 0:
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if (!config->phase_enable0) {
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DBG("Error: Phase capability must be enabled on FTM0\n");
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SYS_LOG_ERR("Phase capability must be "
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"enabled on FTM0");
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return -EINVAL;
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}
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break;
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case 1:
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if (!config->phase_enable2) {
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DBG("Error: Phase capability must be enabled on FTM2\n");
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SYS_LOG_ERR("Phase capability must be "
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"enabled on FTM2");
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return -EINVAL;
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}
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drv_data->phase[1] = on;
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@ -370,14 +365,16 @@ static int pwm_ftm_set_values(struct device *dev, int access_op,
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case 2:
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if (!config->phase_enable4) {
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DBG("Error: Phase capability must be enabled on FTM4\n");
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SYS_LOG_ERR("Phase capability must be "
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"enabled on FTM4");
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return -EINVAL;
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}
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break;
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case 3:
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if (!config->phase_enable6) {
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DBG("Error: Phase capability must be enabled on FTM0\n");
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SYS_LOG_ERR("Phase capability must be "
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"enabled on FTM0");
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return -EINVAL;
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}
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break;
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@ -392,24 +389,25 @@ static int pwm_ftm_set_values(struct device *dev, int access_op,
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sys_read32(PWM_K64_FTM_COMBINE(config->reg_base));
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combine |= 1 << (pwm_pair * 8);
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DBG("pwm_ftm_set_values sys_write32(0x%08x, 0x%08x)..\n",
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SYS_LOG_DBG("sys_write32(0x%08x, 0x%08x)..",
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combine, PWM_K64_FTM_COMBINE(config->reg_base));
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sys_write32(combine, PWM_K64_FTM_COMBINE(config->reg_base));
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DBG("pwm_ftm_set_values sys_write32(0x%08x, 0x%08x)..\n",
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SYS_LOG_DBG("sys_write32(0x%08x, 0x%08x)..",
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on, PWM_K64_FTM_CNV(config->reg_base, channel));
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/* set the on value */
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sys_write32(on, PWM_K64_FTM_CNV(config->reg_base, channel));
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DBG("pwm_ftm_set_values sys_write32(0x%08x, 0x%08x)..\n",
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SYS_LOG_DBG("sys_write32(0x%08x, 0x%08x)..",
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off, PWM_K64_FTM_CNV(config->reg_base, channel+1));
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/* set the off value */
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sys_write32(off, PWM_K64_FTM_CNV(config->reg_base, channel+1));
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#else /*COMBINE_MODE_SUPPORT*/
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DBG("Error: \"on\" value must be zero. Phase is not supported\n");
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SYS_LOG_ERR("\"on\" value must be zero. Phase "
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"is not supported");
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return -EINVAL;
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#endif /*COMBINE_MODE_SUPPORT*/
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@ -429,14 +427,14 @@ static int pwm_ftm_set_values(struct device *dev, int access_op,
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sys_read32(PWM_K64_FTM_COMBINE(config->reg_base));
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combine &= ~(1 << (pwm_pair * 8));
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DBG("pwm_ftm_set_values sys_write32(0x%08x, 0x%08x)..\n",
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SYS_LOG_DBG("sys_write32(0x%08x, 0x%08x)..",
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combine, PWM_K64_FTM_COMBINE(config->reg_base));
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sys_write32(combine, PWM_K64_FTM_COMBINE(config->reg_base));
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/* set the off value */
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DBG("pwm_ftm_set_values sys_write32(0x%08x, 0x%08x)..\n",
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SYS_LOG_DBG("sys_write32(0x%08x, 0x%08x)..",
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off, PWM_K64_FTM_CNV(config->reg_base, channel));
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sys_write32(off, PWM_K64_FTM_CNV(config->reg_base, channel));
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@ -444,7 +442,7 @@ static int pwm_ftm_set_values(struct device *dev, int access_op,
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}
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DBG("pwm_ftm_set_values done.\n");
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SYS_LOG_DBG("done.");
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return 0;
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}
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@ -474,7 +472,7 @@ static int pwm_ftm_set_duty_cycle(struct device *dev, int access_op,
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ARG_UNUSED(access_op);
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DBG("pwm_ftm_set_duty_cycle...\n");
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SYS_LOG_DBG("...");
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if (duty == 0) {
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/* Turn off PWM */
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@ -523,8 +521,7 @@ static int pwm_ftm_set_duty_cycle(struct device *dev, int access_op,
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off = on + config->period * duty / 100;
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DBG("pwm_ftm_set_duty_cycle on=%d, off=%d, "
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"period=%d, duty=%d.\n",
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SYS_LOG_DBG("on=%d, off=%d, period=%d, duty=%d.",
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on, off, config->period, duty);
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/* check for valid off value */
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@ -534,7 +531,7 @@ static int pwm_ftm_set_duty_cycle(struct device *dev, int access_op,
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return pwm_ftm_set_values(dev, access_op, channel, on, off);
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DBG("pwm_ftm_set_duty_cycle done.\n");
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SYS_LOG_DBG("done.");
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}
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@ -570,7 +567,7 @@ static int pwm_ftm_set_phase(struct device *dev, int access_op,
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ARG_UNUSED(access_op);
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DBG("pwm_ftm_set_phase...\n");
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SYS_LOG_DBG("...");
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if ((phase < 0) || (phase > config->period))
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return -ENOTSUP;
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@ -605,7 +602,7 @@ static int pwm_ftm_set_phase(struct device *dev, int access_op,
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return -ENOTSUP;
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}
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DBG("pwm_ftm_set_phase done.\n");
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SYS_LOG_DBG("done.");
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return 0;
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#else /*COMBINE_MODE_SUPPORT*/
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@ -615,7 +612,7 @@ static int pwm_ftm_set_phase(struct device *dev, int access_op,
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ARG_UNUSED(channel);
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ARG_UNUSED(phase);
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DBG("ERROR: non-zero phase is not supported.\n");
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SYS_LOG_ERR("non-zero phase is not supported.");
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return -ENOTSUP;
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#endif /*COMBINE_MODE_SUPPORT*/
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@ -641,7 +638,7 @@ static int pwm_ftm_suspend(struct device *dev, int pm_policy)
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const struct pwm_ftm_config * const config =
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dev->config->config_info;
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DBG("pwm_ftm_suspend...\n");
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SYS_LOG_DBG("...");
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/* set clock source to "no clock selected" */
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@ -653,7 +650,7 @@ static int pwm_ftm_suspend(struct device *dev, int pm_policy)
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sys_write32(reg_val, PWM_K64_FTM_SC(config->reg_base));
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DBG("pwm_ftm_suspend done.\n");
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SYS_LOG_DBG("done.");
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return 0;
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@ -683,7 +680,7 @@ static int pwm_ftm_resume(struct device *dev, int pm_policy)
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const struct pwm_ftm_config * const config =
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dev->config->config_info;
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DBG("pwm_ftm_resume...\n");
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SYS_LOG_DBG("...");
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clock_source = (config->clock_source << PWM_K64_FTM_SC_CLKS_SHIFT) &&
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PWM_K64_FTM_SC_CLKS_MASK;
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@ -696,7 +693,7 @@ static int pwm_ftm_resume(struct device *dev, int pm_policy)
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sys_write32(reg_val, PWM_K64_FTM_SC(config->reg_base));
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DBG("pwm_ftm_resume done.\n");
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SYS_LOG_DBG("done.");
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return 0;
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}
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@ -720,7 +717,7 @@ static struct pwm_driver_api pwm_ftm_drv_api_funcs = {
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int pwm_ftm_init(struct device *dev)
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{
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DBG("pwm_ftm_init...\n");
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SYS_LOG_DBG("...");
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return 0;
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}
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