arm: remove @return doc for void functions

For functions returning nothing, there is no need to document
with @return, as Doxgen complains about "documented empty
return type of ...".

Signed-off-by: Daniel Leung <daniel.leung@intel.com>

arch/arm/core/aarch32/cortex_a_r/irq_init.c

@@ -16,7 +16,6 @@
  *
  * @brief Initialize interrupts
  *
- * @return N/A
  */
 void z_arm_interrupt_init(void)
 {

arch/arm/core/aarch32/cortex_a_r/reboot.c

@@ -19,7 +19,6 @@
  *
  * This routine resets the processor.
  *
- * @return N/A
  */
 
 void __weak sys_arch_reboot(int type)

arch/arm/core/aarch32/cortex_a_r/reset.S

@@ -43,7 +43,6 @@ GTEXT(z_arm_platform_init)
  * When these steps are completed, jump to z_arm_prep_c(), which will finish
  * setting up the system for running C code.
  *
- * @return N/A
  */
 SECTION_SUBSEC_FUNC(TEXT, _reset_section, z_arm_reset)
 SECTION_SUBSEC_FUNC(TEXT, _reset_section, __start)

arch/arm/core/aarch32/cortex_m/exc_exit.S

@@ -47,7 +47,6 @@ GDATA(_kernel)
  * 	z_arm_int_exit();
  * }
  *
- * @return N/A
  */
 
 SECTION_SUBSEC_FUNC(TEXT, _HandlerModeExit, z_arm_int_exit)
@@ -63,7 +62,6 @@ SECTION_SUBSEC_FUNC(TEXT, _HandlerModeExit, z_arm_int_exit)
  *
  * See z_arm_int_exit().
  *
- * @return N/A
  */
 
 SECTION_SUBSEC_FUNC(TEXT, _HandlerModeExit, z_arm_exc_exit)

arch/arm/core/aarch32/cortex_m/fault.c

@@ -353,7 +353,8 @@ static uint32_t mem_manage_fault(z_arch_esf_t *esf, int from_hard_fault,
  *
  * See z_arm_fault_dump() for example.
  *
- * @return N/A
+ * @return error code to identify the fatal error reason.
+ *
  */
 static int bus_fault(z_arch_esf_t *esf, int from_hard_fault, bool *recoverable)
 {
@@ -565,7 +566,6 @@ static uint32_t usage_fault(const z_arch_esf_t *esf)
  *
  * See z_arm_fault_dump() for example.
  *
- * @return N/A
  */
 static void secure_fault(const z_arch_esf_t *esf)
 {
@@ -604,7 +604,6 @@ static void secure_fault(const z_arch_esf_t *esf)
  *
  * See z_arm_fault_dump() for example.
  *
- * @return N/A
  */
 static void debug_monitor(z_arch_esf_t *esf, bool *recoverable)
 {
@@ -725,7 +724,6 @@ static uint32_t hard_fault(z_arch_esf_t *esf, bool *recoverable)
  *
  * See z_arm_fault_dump() for example.
  *
- * @return N/A
  */
 static void reserved_exception(const z_arch_esf_t *esf, int fault)
 {
@@ -1057,7 +1055,6 @@ void z_arm_fault(uint32_t msp, uint32_t psp, uint32_t exc_return,
  *
  * Turns on the desired hardware faults.
  *
- * @return N/A
  */
 void z_arm_fault_init(void)
 {

arch/arm/core/aarch32/cortex_m/irq_init.c

@@ -21,7 +21,6 @@
  * not 0, which they have it set to when coming out of reset. This ensures that
  * interrupt locking via BASEPRI works as expected.
  *
- * @return N/A
  */
 
 void z_arm_interrupt_init(void)

arch/arm/core/aarch32/cortex_m/reset.S

@@ -51,7 +51,6 @@ GDATA(z_main_stack)
  * When these steps are completed, jump to z_arm_prep_c(), which will finish
  * setting up the system for running C code.
  *
- * @return N/A
  */
 
 SECTION_SUBSEC_FUNC(TEXT,_reset_section,z_arm_reset)

arch/arm/core/aarch32/cortex_m/scb.c

@@ -30,7 +30,6 @@
  *
  * This routine resets the processor.
  *
- * @return N/A
  */
 
 void __weak sys_arch_reboot(int type)
@@ -47,7 +46,6 @@ void __weak sys_arch_reboot(int type)
  *
  * This routine clears all ARM MPU region configuration.
  *
- * @return N/A
  */
 void z_arm_clear_arm_mpu_config(void)
 {
@@ -84,7 +82,6 @@ void z_arm_clear_arm_mpu_config(void)
  * This routine resets Cortex-M system control block
  * components and core registers.
  *
- * @return N/A
  */
 void z_arm_init_arch_hw_at_boot(void)
 {

arch/arm/core/aarch32/cpu_idle.S

@@ -35,8 +35,6 @@ GTEXT(arch_cpu_atomic_idle)
  * Only called by arch_kernel_init(). Sets SEVONPEND bit once for the system's
  * duration.
  *
- * @return N/A
- *
  * C function prototype:
  *
  * void z_arm_cpu_idle_init(void);

arch/arm/core/aarch32/irq_manage.c

@@ -60,8 +60,6 @@ int arch_irq_is_enabled(unsigned int irq)
  * The priority is verified if ASSERT_ON is enabled. The maximum number
  * of priority levels is a little complex, as there are some hardware
  * priority levels which are reserved.
- *
- * @return N/A
  */
 void z_arm_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags)
 {
@@ -131,8 +129,6 @@ int arch_irq_is_enabled(unsigned int irq)
  * of priority levels is a little complex, as there are some hardware
  * priority levels which are reserved: three for various types of exceptions,
  * and possibly one additional to support zero latency interrupts.
- *
- * @return N/A
  */
 void z_arm_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags)
 {
@@ -151,7 +147,6 @@ void z_arm_fatal_error(unsigned int reason, const z_arch_esf_t *esf);
  * Installed in all _sw_isr_table slots at boot time. Throws an error if
  * called.
  *
- * @return N/A
  */
 void z_irq_spurious(const void *unused)
 {
@@ -270,7 +265,6 @@ int irq_target_state_is_secure(unsigned int irq)
  * - Bits corresponding to un-implemented interrupts are RES0, so writes
  *   will be ignored.
  *
- * @return N/A
 */
 void irq_target_state_set_all_non_secure(void)
 {

arch/arm/core/aarch32/isr_wrapper.S

@@ -42,7 +42,6 @@ GTEXT(z_arm_int_exit)
  * z_arm_pendsv()) and pends the PendSV exception if so: the latter will
  * perform the context switch itself.
  *
- * @return N/A
  */
 SECTION_FUNC(TEXT, _isr_wrapper)
 

arch/arm/core/aarch32/nmi.c

@@ -36,7 +36,6 @@ static _NmiHandler_t handler = z_SysNmiOnReset;
  * The default handler outputs a error message and reboots the target. It is
  * installed by calling z_arm_nmi_init();
  *
- * @return N/A
  */
 
 static void DefaultHandler(void)
@@ -54,7 +53,6 @@ static void DefaultHandler(void)
  * handler that reboots the target. It should be installed after the console is
  * initialized.
  *
- * @return N/A
  */
 
 void z_arm_nmi_init(void)
@@ -70,7 +68,6 @@ void z_arm_nmi_init(void)
  * handler that reboots. It should be installed after the console is
  * initialized if it is meant to output to the console.
  *
- * @return N/A
  */
 
 void z_NmiHandlerSet(void (*pHandler)(void))
@@ -85,7 +82,6 @@ void z_NmiHandlerSet(void (*pHandler)(void))
  *
  * Simply call what is installed in 'static void(*handler)(void)'.
  *
- * @return N/A
  */
 
 void z_arm_nmi(void)

arch/arm/core/aarch32/prep_c.c

@@ -173,7 +173,6 @@ extern FUNC_NORETURN void z_cstart(void);
  *
  * This routine prepares for the execution of and runs C code.
  *
- * @return N/A
  */
 void z_arm_prep_c(void)
 {

arch/arm/core/aarch32/swap_helper.S

@@ -413,7 +413,6 @@ _thread_irq_disabled:
  * - Kernel run-time exceptions
  * - System Calls (User mode)
  *
- * @return N/A
  */
 SECTION_FUNC(TEXT, z_arm_svc)
   /* Use EXC_RETURN state to find out if stack frame is on the
@@ -614,7 +613,6 @@ valid_syscall_id:
  * - IRQ offloading
  * - Kernel run-time exceptions
  *
- * @return N/A
  */
 SECTION_FUNC(TEXT, z_arm_svc)
 #if defined(CONFIG_USERSPACE)

arch/arm/include/aarch32/cortex_a_r/exc.h

@@ -59,7 +59,6 @@ static ALWAYS_INLINE bool z_arm_preempted_thread_in_user_mode(const z_arch_esf_t
  *
  * Enable fault exceptions.
  *
- * @return N/A
  */
 static ALWAYS_INLINE void z_arm_exc_setup(void)
 {
@@ -70,7 +69,6 @@ static ALWAYS_INLINE void z_arm_exc_setup(void)
  *
  * Clear out exceptions for Mem, Bus, Usage and Hard Faults
  *
- * @return N/A
  */
 static ALWAYS_INLINE void z_arm_clear_faults(void)
 {

arch/arm/include/aarch32/cortex_a_r/stack.h

@@ -32,7 +32,6 @@ extern void z_arm_init_stacks(void);
  *
  * On Cortex-A and Cortex-R, the interrupt stack is set up by reset.S
  *
- * @return N/A
  */
 static ALWAYS_INLINE void z_arm_interrupt_stack_setup(void)
 {

arch/arm/include/aarch32/cortex_a_r/tcm.h

@@ -32,7 +32,6 @@ extern "C" {
  *
  * This function shall only be called in Privileged mode.
  *
- * @return N/A
  */
 void z_arm_tcm_disable_ecc(void);
 

arch/arm/include/aarch32/cortex_m/dwt.h

@@ -125,8 +125,6 @@ static inline uint32_t z_arm_dwt_get_cycles(void)
  * @brief Reset and start the DWT cycle counter
  *
  * This routine starts the cycle counter and resets its value to zero.
- *
- * @return N/A
  */
 static inline void z_arm_dwt_cycle_count_start(void)
 {
@@ -140,8 +138,6 @@ static inline void z_arm_dwt_cycle_count_start(void)
  * This routine enables the DebugMonitor handler to service
  * data watchpoint events coming from DWT. The routine sets
  * the DebugMonitor exception priority to highest possible.
- *
- * @return N/A
  */
 static inline void z_arm_dwt_enable_debug_monitor(void)
 {

arch/arm/include/aarch32/cortex_m/exc.h

@@ -93,8 +93,6 @@ static ALWAYS_INLINE bool z_arm_preempted_thread_in_user_mode(const z_arch_esf_t
  * Set PendSV priority to lowest possible.
  *
  * Enable fault exceptions.
- *
- * @return N/A
  */
 static ALWAYS_INLINE void z_arm_exc_setup(void)
 {
@@ -167,8 +165,6 @@ static ALWAYS_INLINE void z_arm_exc_setup(void)
  * @brief Clear Fault exceptions
  *
  * Clear out exceptions for Mem, Bus, Usage and Hard Faults
- *
- * @return N/A
  */
 static ALWAYS_INLINE void z_arm_clear_faults(void)
 {

arch/arm/include/aarch32/cortex_m/stack.h

@@ -36,7 +36,6 @@ K_KERNEL_STACK_ARRAY_EXTERN(z_interrupt_stacks, CONFIG_MP_NUM_CPUS,
  * On Cortex-M, the interrupt stack is registered in the MSP (main stack
  * pointer) register, and switched to automatically when taking an exception.
  *
- * @return N/A
  */
 static ALWAYS_INLINE void z_arm_interrupt_stack_setup(void)
 {

arch/arm/include/aarch32/cortex_m/tz.h

@@ -63,7 +63,6 @@ typedef struct tz_nonsecure_setup_conf {
  * This function shall be called before the Secure Firmware may transition
  * to Non-Secure state.
  *
- * @return N/A
  */
 void tz_nonsecure_state_setup(const tz_nonsecure_setup_conf_t *p_ns_conf);
 
@@ -82,7 +81,6 @@ void tz_nonsecure_state_setup(const tz_nonsecure_setup_conf_t *p_ns_conf);
  * This function shall only be called from Secure state.
  * Only ARMv8-M Mainline implementations have Non-Secure MSPLIM instance.
  *
- * @return N/A
  */
 void tz_nonsecure_msplim_set(uint32_t val);
 
@@ -99,7 +97,6 @@ void tz_nonsecure_msplim_set(uint32_t val);
  * This function shall only be called from Secure state.
  * Only ARMv8-M Mainline implementations have Non-Secure PSPLIM instance.
  *
- * @return N/A
  */
 void tz_nonsecure_psplim_set(uint32_t val);
 
@@ -117,8 +114,6 @@ void tz_nonsecure_psplim_set(uint32_t val);
  * Note:
  *
  * This function shall only be called from Secure state.
- *
- * @return N/A
  */
 void tz_nonsecure_system_reset_req_block(int block);
 
@@ -134,8 +129,6 @@ void tz_nonsecure_system_reset_req_block(int block);
  * Note:
  *
  * This function shall only be called from Secure state.
- *
- * @return N/A
  */
 void tz_nonsecure_exception_prio_config(int secure_boost);
 
@@ -162,8 +155,6 @@ void tz_nonsecure_exception_prio_config(int secure_boost);
  * - If secure_state is set to 1 (Secure), all Non-Secure HardFaults are
  * escalated to Secure HardFaults.
  * - BusFault is present only if the Main Extension is implemented.
- *
- * @return N/A
  */
 void tz_nbanked_exception_target_state_set(int secure_state);
 
@@ -178,8 +169,6 @@ void tz_nbanked_exception_target_state_set(int secure_state);
  * Note:
  *
  * This function shall only be called from Secure state.
- *
- * @return N/A
  */
 void tz_nonsecure_fpu_access_enable(void);
 #endif /* CONFIG_ARMV7_M_ARMV8_M_FP */
@@ -209,7 +198,6 @@ void tz_nonsecure_fpu_access_enable(void);
  * This function shall be called before the Secure Firmware may transition
  * to Non-Secure state.
  *
- * @return N/A
  */
 void tz_sau_configure(int enable, int allns);
 

arch/arm64/core/prep_c.c

@@ -39,7 +39,6 @@ static inline void z_arm64_bss_zero(void)
  *
  * This routine prepares for the execution of and runs C code.
  *
- * @return N/A
  */
 void z_arm64_prep_c(void)
 {

soc/arm/nxp_imx/rt/soc_rt10xx.c

@@ -108,11 +108,7 @@ const __imx_boot_ivt_section ivt image_vector_table = {
 #endif
 
 /**
- *
  * @brief Initialize the system clock
- *
- * @return N/A
- *
  */
 static ALWAYS_INLINE void clock_init(void)
 {

soc/arm/nxp_imx/rt/soc_rt11xx.c

@@ -120,11 +120,7 @@ const __imx_boot_ivt_section ivt image_vector_table = {
 #endif
 
 /**
- *
  * @brief Initialize the system clock
- *
- * @return N/A
- *
  */
 static ALWAYS_INLINE void clock_init(void)
 {

soc/arm/nxp_imx/rt6xx/soc.c

@@ -172,11 +172,7 @@ static void usb_device_clock_init(void)
 #endif
 
 /**
- *
  * @brief Initialize the system clock
- *
- * @return N/A
- *
  */
 static ALWAYS_INLINE void clock_init(void)
 {

soc/arm/nxp_kinetis/k2x/soc.c

@@ -81,8 +81,6 @@ static const sim_clock_config_t simConfig = {
  * PLL Engaged External (PEE) mode and generate the maximum 120 MHz system
  * clock.
  *
- * @return N/A
- *
  */
 static ALWAYS_INLINE void clock_init(void)
 {

soc/arm/nxp_kinetis/k2x/wdog.S

@@ -33,7 +33,6 @@ GTEXT(z_arm_watchdog_init)
  *
  * This routine will disable the watchdog timer.
  *
- * @return N/A
  */
 
 SECTION_FUNC(TEXT,z_arm_watchdog_init)

soc/arm/nxp_kinetis/k6x/soc.c

@@ -86,8 +86,6 @@ static const sim_clock_config_t simConfig = {
  * PLL Engaged External (PEE) mode and generate the maximum 120 MHz system
  * clock.
  *
- * @return N/A
- *
  */
 static ALWAYS_INLINE void clock_init(void)
 {

soc/arm/nxp_kinetis/k6x/wdog.S

@@ -33,7 +33,6 @@ GTEXT(z_arm_watchdog_init)
  *
  * This routine will disable the watchdog timer.
  *
- * @return N/A
  */
 
 SECTION_FUNC(TEXT,z_arm_watchdog_init)

soc/arm/nxp_kinetis/k8x/wdog.S

@@ -33,7 +33,6 @@ GTEXT(z_arm_watchdog_init)
  *
  * This routine will disable the watchdog timer.
  *
- * @return N/A
  */
 
 SECTION_FUNC(TEXT,z_arm_watchdog_init)

soc/arm/nxp_kinetis/kv5x/wdog.S

@@ -33,7 +33,6 @@ GTEXT(z_arm_watchdog_init)
  *
  * This routine will disable the watchdog timer.
  *
- * @return N/A
  */
 
 SECTION_FUNC(TEXT,z_arm_watchdog_init)

soc/arm/nxp_kinetis/kwx/soc_kw2xd.c

@@ -80,8 +80,6 @@ static const sim_clock_config_t simConfig = {
  * depends on the state of GPIO5 during transceiver reset. The frequency
  * will be 4 MHz if the GPIO5 pin is low, otherwise it will be 32.78689 kHz.
  *
- * @return N/A
- *
  */
 static void set_modem_clock(void)
 {
@@ -118,8 +116,6 @@ static void set_modem_clock(void)
  * PLL Engaged External (PEE) mode and generate the maximum 48 MHz system
  * clock.
  *
- * @return N/A
- *
  */
 static ALWAYS_INLINE void clock_init(void)
 {

soc/arm/nxp_kinetis/kwx/wdog.S

@@ -33,7 +33,6 @@ GTEXT(z_arm_watchdog_init)
  *
  * This routine will disable the watchdog timer.
  *
- * @return N/A
  */
 
 SECTION_FUNC(TEXT,z_arm_watchdog_init)

soc/arm/nxp_lpc/lpc54xxx/soc.c

@@ -32,8 +32,6 @@
  *
  * @brief Initialize the system clock
  *
- * @return N/A
- *
  */
 #define CPU_FREQ DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency)
 
@@ -144,7 +142,9 @@ static const char core_m0[] = {
  * @brief Slave Init
  *
  * This routine boots the secondary core
- * @return N/A
+ *
+ * @retval 0 on success.
+ *
  */
 /* This function is also called at deep sleep resume. */
 int _slave_init(const struct device *arg)

soc/arm/nxp_lpc/lpc55xxx/soc.c

@@ -54,8 +54,6 @@ const pll_setup_t pll0Setup = {
  *
  * @brief Initialize the system clock
  *
- * @return N/A
- *
  */
 
 static ALWAYS_INLINE void clock_init(void)
@@ -234,7 +232,9 @@ SYS_INIT(nxp_lpc55xxx_init, PRE_KERNEL_1, 0);
  * @brief Second Core Init
  *
  * This routine boots the secondary core
- * @return N/A
+ *
+ * @retval 0 on success.
+ *
  */
 /* This function is also called at deep sleep resume. */
 int _second_core_init(const struct device *arg)

soc/arm/silabs_exx32/common/soc.c

@@ -36,9 +36,6 @@ static CMU_LFXOInit_TypeDef lfxoInit = CMU_LFXOINIT_DEFAULT;
 
 /**
  * @brief Initialize the system clock
- *
- * @return N/A
- *
  */
 static ALWAYS_INLINE void clock_init(void)
 {

soc/arm/ti_lm3s6965/sys_arch_reboot.c

@@ -15,7 +15,6 @@
  *
  * This routine resets the processor.
  *
- * @return N/A
  */
 
 void sys_arch_reboot(int type)