x86: unify stack macro definitions
Introduce a new header thread_stack.h which does the right thing for both 32-bit and 64-bit x86. Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This commit is contained in:
Andrew Boie
Andrew Boie
parent
10a1b25da6
commit
a9e0d14c57
4 changed files with 232 additions and 203 deletions
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@ -16,6 +16,7 @@
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#include <stdbool.h>
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#include <irq.h>
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#include <arch/x86/mmustructs.h>
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#include <arch/x86/thread_stack.h>
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static ALWAYS_INLINE void z_arch_irq_unlock(unsigned int key)
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{
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@ -54,18 +54,8 @@
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extern "C" {
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#endif
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/* interrupt/exception/error related definitions */
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/*
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* The TCS must be aligned to the same boundary as that used by the floating
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* point register set. This applies even for threads that don't initially
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* use floating point, since it is possible to enable floating point support
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* later on.
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*/
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#define STACK_ALIGN FP_REG_SET_ALIGN
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typedef struct s_isrList {
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/** Address of ISR/stub */
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void *fnc;
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@ -353,176 +343,6 @@ extern void k_float_enable(struct k_thread *thread, unsigned int options);
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extern struct task_state_segment _main_tss;
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#endif
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#ifdef CONFIG_USERSPACE
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/* We need a set of page tables for each thread in the system which runs in
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* user mode. For each thread, we have:
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*
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* - a toplevel PDPT
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* - a set of page directories for the memory range covered by system RAM
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* - a set of page tbales for the memory range covered by system RAM
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*
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* Directories and tables for memory ranges outside of system RAM will be
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* shared and not thread-specific.
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*
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* NOTE: We are operating under the assumption that memory domain partitions
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* will not be configured which grant permission to address ranges outside
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* of system RAM.
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*
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* Each of these page tables will be programmed to reflect the memory
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* permission policy for that thread, which will be the union of:
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*
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* - The boot time memory regions (text, rodata, and so forth)
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* - The thread's stack buffer
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* - Partitions in the memory domain configuration (if a member of a
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* memory domain)
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*
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* The PDPT is fairly small singleton on x86 PAE (32 bytes) and also must
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* be aligned to 32 bytes, so we place it at the highest addresses of the
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* page reserved for the privilege elevation stack.
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*
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* The page directories and tables require page alignment so we put them as
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* additional fields in the stack object, using the below macros to compute how
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* many pages we need.
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*/
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/* Define a range [Z_X86_PT_START, Z_X86_PT_END) which is the memory range
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* covered by all the page tables needed for system RAM
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*/
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#define Z_X86_PT_START ((u32_t)ROUND_DOWN(DT_PHYS_RAM_ADDR, Z_X86_PT_AREA))
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#define Z_X86_PT_END ((u32_t)ROUND_UP(DT_PHYS_RAM_ADDR + \
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(DT_RAM_SIZE * 1024U), \
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Z_X86_PT_AREA))
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/* Number of page tables needed to cover system RAM. Depends on the specific
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* bounds of system RAM, but roughly 1 page table per 2MB of RAM */
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#define Z_X86_NUM_PT ((Z_X86_PT_END - Z_X86_PT_START) / Z_X86_PT_AREA)
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/* Same semantics as above, but for the page directories needed to cover
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* system RAM.
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*/
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#define Z_X86_PD_START ((u32_t)ROUND_DOWN(DT_PHYS_RAM_ADDR, Z_X86_PD_AREA))
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#define Z_X86_PD_END ((u32_t)ROUND_UP(DT_PHYS_RAM_ADDR + \
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(DT_RAM_SIZE * 1024U), \
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Z_X86_PD_AREA))
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/* Number of page directories needed to cover system RAM. Depends on the
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* specific bounds of system RAM, but roughly 1 page directory per 1GB of RAM */
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#define Z_X86_NUM_PD ((Z_X86_PD_END - Z_X86_PD_START) / Z_X86_PD_AREA)
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/* Number of pages we need to reserve in the stack for per-thread page tables */
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#define Z_X86_NUM_TABLE_PAGES (Z_X86_NUM_PT + Z_X86_NUM_PD)
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#else
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/* If we're not implementing user mode, then the MMU tables don't get changed
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* on context switch and we don't need any per-thread page tables
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*/
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#define Z_X86_NUM_TABLE_PAGES 0U
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#endif /* CONFIG_USERSPACE */
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#define Z_X86_THREAD_PT_AREA (Z_X86_NUM_TABLE_PAGES * MMU_PAGE_SIZE)
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#if defined(CONFIG_HW_STACK_PROTECTION) || defined(CONFIG_USERSPACE)
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#define Z_X86_STACK_BASE_ALIGN MMU_PAGE_SIZE
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#else
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#define Z_X86_STACK_BASE_ALIGN STACK_ALIGN
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#endif
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#ifdef CONFIG_USERSPACE
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/* If user mode enabled, expand any stack size to fill a page since that is
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* the access control granularity and we don't want other kernel data to
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* unintentionally fall in the latter part of the page
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*/
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#define Z_X86_STACK_SIZE_ALIGN MMU_PAGE_SIZE
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#else
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#define Z_X86_STACK_SIZE_ALIGN 1
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#endif
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struct z_x86_kernel_stack_data {
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/* For 32-bit, a single four-entry page directory pointer table, that
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* needs to be aligned to 32 bytes.
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*/
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struct x86_page_tables ptables;
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} __aligned(0x20);
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/* With both hardware stack protection and userspace enabled, stacks are
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* arranged as follows:
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*
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* High memory addresses
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* +-----------------------------------------+
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* | Thread stack (varies) |
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* +-----------------------------------------+
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* | PDPT (32 bytes) |
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* | Privilege elevation stack (4064 bytes) |
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* +-----------------------------------------+
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* | Guard page (4096 bytes) |
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* +-----------------------------------------+
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* | User page tables (Z_X86_THREAD_PT_AREA) |
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* +-----------------------------------------+
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* Low Memory addresses
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*
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* Privilege elevation stacks are fixed-size. All the pages containing the
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* thread stack are marked as user-accessible. The guard page is marked
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* read-only to catch stack overflows in supervisor mode.
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*
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* If a thread starts in supervisor mode, the page containing the PDPT and
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* privilege elevation stack is also marked read-only.
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*
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* If a thread starts in, or drops down to user mode, the privilege stack page
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* will be marked as present, supervior-only. The PDPT will be initialized and
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* used as the active page tables when that thread is active.
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*
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* If KPTI is not enabled, the _main_tss.esp0 field will always be updated
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* updated to point to the top of the privilege elevation stack. Otherwise
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* _main_tss.esp0 always points to the trampoline stack, which handles the
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* page table switch to the kernel PDPT and transplants context to the
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* privileged mode stack.
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*/
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struct z_x86_thread_stack_header {
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#ifdef CONFIG_USERSPACE
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char page_tables[Z_X86_THREAD_PT_AREA];
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#endif
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#ifdef CONFIG_HW_STACK_PROTECTION
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char guard_page[MMU_PAGE_SIZE];
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#endif
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#ifdef CONFIG_USERSPACE
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char privilege_stack[MMU_PAGE_SIZE -
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sizeof(struct z_x86_kernel_stack_data)];
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struct z_x86_kernel_stack_data kernel_data;
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#endif
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} __packed __aligned(Z_X86_STACK_SIZE_ALIGN);
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#define Z_ARCH_THREAD_STACK_RESERVED \
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((u32_t)sizeof(struct z_x86_thread_stack_header))
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#define Z_ARCH_THREAD_STACK_DEFINE(sym, size) \
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struct _k_thread_stack_element __noinit \
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__aligned(Z_X86_STACK_BASE_ALIGN) \
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sym[ROUND_UP((size), Z_X86_STACK_SIZE_ALIGN) + \
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Z_ARCH_THREAD_STACK_RESERVED]
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#define Z_ARCH_THREAD_STACK_LEN(size) \
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(ROUND_UP((size), \
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MAX(Z_X86_STACK_BASE_ALIGN, \
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Z_X86_STACK_SIZE_ALIGN)) + \
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Z_ARCH_THREAD_STACK_RESERVED)
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#define Z_ARCH_THREAD_STACK_ARRAY_DEFINE(sym, nmemb, size) \
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struct _k_thread_stack_element __noinit \
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__aligned(Z_X86_STACK_BASE_ALIGN) \
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sym[nmemb][Z_ARCH_THREAD_STACK_LEN(size)]
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#define Z_ARCH_THREAD_STACK_MEMBER(sym, size) \
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struct _k_thread_stack_element __aligned(Z_X86_STACK_BASE_ALIGN) \
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sym[ROUND_UP((size), Z_X86_STACK_SIZE_ALIGN) + \
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Z_ARCH_THREAD_STACK_RESERVED]
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#define Z_ARCH_THREAD_STACK_SIZEOF(sym) \
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(sizeof(sym) - Z_ARCH_THREAD_STACK_RESERVED)
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#define Z_ARCH_THREAD_STACK_BUFFER(sym) \
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((char *)((sym) + Z_ARCH_THREAD_STACK_RESERVED))
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#if CONFIG_X86_KERNEL_OOPS
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#define Z_ARCH_EXCEPT(reason_p) do { \
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__asm__ volatile( \
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@ -7,9 +7,7 @@
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#define ZEPHYR_INCLUDE_ARCH_X86_INTEL64_ARCH_H_
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#include <arch/x86/intel64/thread.h>
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#define STACK_ALIGN 16
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#define STACK_SIZE_ALIGN 16
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#include <arch/x86/thread_stack.h>
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#if CONFIG_ISR_STACK_SIZE != (CONFIG_ISR_SUBSTACK_SIZE * CONFIG_ISR_DEPTH)
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#error "Check ISR stack configuration (CONFIG_ISR_*)"
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@ -20,26 +18,6 @@
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#endif
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#ifndef _ASMLANGUAGE
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#define Z_ARCH_THREAD_STACK_LEN(size) (ROUND_UP((size), STACK_SIZE_ALIGN))
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#define Z_ARCH_THREAD_STACK_DEFINE(sym, size) \
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struct _k_thread_stack_element __noinit \
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__aligned(STACK_ALIGN) \
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sym[Z_ARCH_THREAD_STACK_LEN(size)]
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#define Z_ARCH_THREAD_STACK_ARRAY_DEFINE(sym, nmemb, size) \
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struct _k_thread_stack_element __noinit \
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__aligned(STACK_ALIGN) \
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sym[nmemb][Z_ARCH_THREAD_STACK_LEN(size)]
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#define Z_ARCH_THREAD_STACK_MEMBER(sym, size) \
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struct _k_thread_stack_element __aligned(STACK_ALIGN) \
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sym[Z_ARCH_THREAD_STACK_LEN(size)]
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#define Z_ARCH_THREAD_STACK_SIZEOF(sym) sizeof(sym)
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#define Z_ARCH_THREAD_STACK_BUFFER(sym) ((char *) sym)
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static ALWAYS_INLINE unsigned int z_arch_irq_lock(void)
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{
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unsigned long key;
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230
include/arch/x86/thread_stack.h
Normal file
230
include/arch/x86/thread_stack.h
Normal file
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@ -0,0 +1,230 @@
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/*
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* Copyright (c) 2019 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_ARCH_X86_THREAD_STACK_H
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#define ZEPHYR_INCLUDE_ARCH_X86_THREAD_STACK_H
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#include <arch/x86/mmustructs.h>
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#ifdef CONFIG_X86_64
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#define STACK_ALIGN 16UL
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#else
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#define STACK_ALIGN 4UL
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#endif
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#ifdef CONFIG_USERSPACE
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/* We need a set of page tables for each thread in the system which runs in
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* user mode. For each thread, we have:
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*
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* - On 32-bit
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* - a toplevel PDPT
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* - On 64-bit
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* - a toplevel PML4
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* - a set of PDPTs for the memory range covered by system RAM
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* - On all modes:
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* - a set of page directories for the memory range covered by system RAM
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* - a set of page tbales for the memory range covered by system RAM
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*
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* Directories and tables for memory ranges outside of system RAM will be
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* shared and not thread-specific.
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*
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* NOTE: We are operating under the assumption that memory domain partitions
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* will not be configured which grant permission to address ranges outside
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* of system RAM.
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*
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* Each of these page tables will be programmed to reflect the memory
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* permission policy for that thread, which will be the union of:
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*
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* - The boot time memory regions (text, rodata, and so forth)
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* - The thread's stack buffer
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* - Partitions in the memory domain configuration (if a member of a
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* memory domain)
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*
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* The PDPT is fairly small singleton on x86 PAE (32 bytes) and also must
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* be aligned to 32 bytes, so we place it at the highest addresses of the
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* page reserved for the privilege elevation stack. On 64-bit all table
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* entities up to and including the PML4 are page-sized.
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*
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* The page directories and tables require page alignment so we put them as
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* additional fields in the stack object, using the below macros to compute how
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* many pages we need.
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*/
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/* Define a range [Z_X86_PT_START, Z_X86_PT_END) which is the memory range
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* covered by all the page tables needed for system RAM
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*/
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#define Z_X86_PT_START ((u32_t)ROUND_DOWN(DT_PHYS_RAM_ADDR, Z_X86_PT_AREA))
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#define Z_X86_PT_END ((u32_t)ROUND_UP(DT_PHYS_RAM_ADDR + \
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(DT_RAM_SIZE * 1024UL), \
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Z_X86_PT_AREA))
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/* Number of page tables needed to cover system RAM. Depends on the specific
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* bounds of system RAM, but roughly 1 page table per 2MB of RAM
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*/
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#define Z_X86_NUM_PT ((Z_X86_PT_END - Z_X86_PT_START) / Z_X86_PT_AREA)
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/* Same semantics as above, but for the page directories needed to cover
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* system RAM.
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*/
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#define Z_X86_PD_START ((u32_t)ROUND_DOWN(DT_PHYS_RAM_ADDR, Z_X86_PD_AREA))
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#define Z_X86_PD_END ((u32_t)ROUND_UP(DT_PHYS_RAM_ADDR + \
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(DT_RAM_SIZE * 1024UL), \
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Z_X86_PD_AREA))
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/* Number of page directories needed to cover system RAM. Depends on the
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* specific bounds of system RAM, but roughly 1 page directory per 1GB of RAM
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*/
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#define Z_X86_NUM_PD ((Z_X86_PD_END - Z_X86_PD_START) / Z_X86_PD_AREA)
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#ifdef CONFIG_X86_64
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/* Same semantics as above, but for the page directory pointer tables needed
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* to cover system RAM. On 32-bit there is just one 4-entry PDPT.
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*/
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#define Z_X86_PDPT_START ((u32_t)ROUND_DOWN(DT_PHYS_RAM_ADDR, \
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Z_X86_PD_AREA))
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#define Z_X86_PDPT_END ((u32_t)ROUND_UP(DT_PHYS_RAM_ADDR + \
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(DT_RAM_SIZE * 1024UL), \
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Z_X86_PDPT_AREA))
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/* Number of PDPTs needed to cover system RAM. Depends on the
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* specific bounds of system RAM, but roughly 1 PDPT per 512GB of RAM
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*/
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#define Z_X86_NUM_PDPT ((Z_X86_PDPT_END - Z_X86_PDPT_START) / Z_X86_PDPT_AREA)
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/* All pages needed for page tables, using computed values plus one more for
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* the top-level PML4
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*/
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#define Z_X86_NUM_TABLE_PAGES (Z_X86_NUM_PT + Z_X86_NUM_PD + \
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Z_X86_NUM_PDPT + 1)
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#else /* !CONFIG_X86_64 */
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/* Number of pages we need to reserve in the stack for per-thread page tables */
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#define Z_X86_NUM_TABLE_PAGES (Z_X86_NUM_PT + Z_X86_NUM_PD)
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#endif /* CONFIG_X86_64 */
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#else /* !CONFIG_USERSPACE */
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/* If we're not implementing user mode, then the MMU tables don't get changed
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* on context switch and we don't need any per-thread page tables
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*/
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#define Z_X86_NUM_TABLE_PAGES 0UL
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#endif /* CONFIG_USERSPACE */
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#define Z_X86_THREAD_PT_AREA (Z_X86_NUM_TABLE_PAGES * MMU_PAGE_SIZE)
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#if defined(CONFIG_HW_STACK_PROTECTION) || defined(CONFIG_USERSPACE)
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#define Z_X86_STACK_BASE_ALIGN MMU_PAGE_SIZE
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#else
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#define Z_X86_STACK_BASE_ALIGN STACK_ALIGN
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#endif
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#ifdef CONFIG_USERSPACE
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/* If user mode enabled, expand any stack size to fill a page since that is
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* the access control granularity and we don't want other kernel data to
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* unintentionally fall in the latter part of the page
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*/
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#define Z_X86_STACK_SIZE_ALIGN MMU_PAGE_SIZE
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#else
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#define Z_X86_STACK_SIZE_ALIGN STACK_ALIGN
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#endif
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#ifndef _ASMLANGUAGE
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#ifndef CONFIG_X86_64
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struct z_x86_kernel_stack_data {
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/* For 32-bit, a single four-entry page directory pointer table, that
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* needs to be aligned to 32 bytes.
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*
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* 64-bit all the page table entities up to and including the PML4
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* are page-aligned and we just reserve room for them in
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* Z_X86_THREAD_PT_AREA.
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*/
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struct x86_page_tables ptables;
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} __aligned(0x20);
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#endif /* !CONFIG_X86_64 */
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/* With both hardware stack protection and userspace enabled, stacks are
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* arranged as follows:
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*
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* High memory addresses
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* +-----------------------------------------+
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* | Thread stack (varies) |
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* +-----------------------------------------+
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* | PDPT (32 bytes, 32-bit only) |
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* | Privilege elevation stack |
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* | (4064 or 4096 bytes) |
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* +-----------------------------------------+
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* | Guard page (4096 bytes) |
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* +-----------------------------------------+
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* | User page tables (Z_X86_THREAD_PT_AREA) |
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* +-----------------------------------------+
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* Low Memory addresses
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*
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* Privilege elevation stacks are fixed-size. All the pages containing the
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* thread stack are marked as user-accessible. The guard page is marked
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* read-only to catch stack overflows in supervisor mode.
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*
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* If a thread starts in supervisor mode, the page containing the PDPT and/or
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* privilege elevation stack is also marked read-only.
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*
|
||||
* If a thread starts in, or drops down to user mode, the privilege stack page
|
||||
* will be marked as present, supervior-only. The page tables will be
|
||||
* initialized and used as the active page tables when that thread is active.
|
||||
*
|
||||
* If KPTI is not enabled, the _main_tss.esp0 field will always be updated
|
||||
* updated to point to the top of the privilege elevation stack. Otherwise
|
||||
* _main_tss.esp0 always points to the trampoline stack, which handles the
|
||||
* page table switch to the kernel PDPT and transplants context to the
|
||||
* privileged mode stack.
|
||||
*/
|
||||
struct z_x86_thread_stack_header {
|
||||
#ifdef CONFIG_USERSPACE
|
||||
char page_tables[Z_X86_THREAD_PT_AREA];
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_HW_STACK_PROTECTION
|
||||
char guard_page[MMU_PAGE_SIZE];
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USERSPACE
|
||||
#ifdef CONFIG_X86_64
|
||||
char privilege_stack[MMU_PAGE_SIZE];
|
||||
#else
|
||||
char privilege_stack[MMU_PAGE_SIZE -
|
||||
sizeof(struct z_x86_kernel_stack_data)];
|
||||
|
||||
struct z_x86_kernel_stack_data kernel_data;
|
||||
#endif /* CONFIG_X86_64 */
|
||||
#endif /* CONFIG_USERSPACE */
|
||||
} __packed __aligned(Z_X86_STACK_BASE_ALIGN);
|
||||
|
||||
#define Z_ARCH_THREAD_STACK_RESERVED \
|
||||
((u32_t)sizeof(struct z_x86_thread_stack_header))
|
||||
|
||||
#define Z_ARCH_THREAD_STACK_DEFINE(sym, size) \
|
||||
struct _k_thread_stack_element __noinit \
|
||||
__aligned(Z_X86_STACK_BASE_ALIGN) \
|
||||
sym[ROUND_UP((size), Z_X86_STACK_SIZE_ALIGN) + \
|
||||
Z_ARCH_THREAD_STACK_RESERVED]
|
||||
|
||||
#define Z_ARCH_THREAD_STACK_LEN(size) \
|
||||
(ROUND_UP((size), \
|
||||
MAX(Z_X86_STACK_BASE_ALIGN, \
|
||||
Z_X86_STACK_SIZE_ALIGN)) + \
|
||||
Z_ARCH_THREAD_STACK_RESERVED)
|
||||
|
||||
#define Z_ARCH_THREAD_STACK_ARRAY_DEFINE(sym, nmemb, size) \
|
||||
struct _k_thread_stack_element __noinit \
|
||||
__aligned(Z_X86_STACK_BASE_ALIGN) \
|
||||
sym[nmemb][Z_ARCH_THREAD_STACK_LEN(size)]
|
||||
|
||||
#define Z_ARCH_THREAD_STACK_MEMBER(sym, size) \
|
||||
struct _k_thread_stack_element __aligned(Z_X86_STACK_BASE_ALIGN) \
|
||||
sym[ROUND_UP((size), Z_X86_STACK_SIZE_ALIGN) + \
|
||||
Z_ARCH_THREAD_STACK_RESERVED]
|
||||
|
||||
#define Z_ARCH_THREAD_STACK_SIZEOF(sym) \
|
||||
(sizeof(sym) - Z_ARCH_THREAD_STACK_RESERVED)
|
||||
|
||||
#define Z_ARCH_THREAD_STACK_BUFFER(sym) \
|
||||
((char *)((sym) + Z_ARCH_THREAD_STACK_RESERVED))
|
||||
|
||||
#endif /* !_ASMLANGUAGE */
|
||||
#endif /* ZEPHYR_INCLUDE_ARCH_X86_THREAD_STACK_H */
|
||||
Loading…
Add table
Add a link
Reference in a new issue