From a9366c76e8bdaff9e4f98d30169d90ce5306d2b0 Mon Sep 17 00:00:00 2001 From: Mulin Chao Date: Mon, 26 Apr 2021 02:17:39 -0700 Subject: [PATCH] dts: npcx: arrange device-tree files of npcx7 series. Arrange device-tree files of npcx7 series by following steps: 1. Move device-tree declarations of npcx family to npcx.dtsi. 2. Leave specific device declarations of npcx7 series to npcx7.dtsi. 3. Move chip series related mapping tables such as npcx7-miwus-wui-map.dtsi and so on to npcx/npcx7 folder. 4. Move common device-tree declarations used in each npcx series to npcx-miwus-wui-map.dtsi and so on to npcx folder. Then, the npcx device-tree folders are arranged to: dts/arm/nuvoton |--npcx | |--npcx7 | | |--npcx7-miwus-wui-map.dtsi | | |--npcx7-alts-map.dtsi | | |--..... | |--npcx-miwus-wui-map.dtsi | |--npcx-alts-map.dtsi | |--..... | |--npcx.dtsi |--npcx7.dtsi Signed-off-by: Jun Lin Signed-off-by: Mulin Chao --- dts/arm/nuvoton/npcx.dtsi | 628 ++++++++++++++++++ ...npcx7-alts-map.dtsi => npcx-alts-map.dtsi} | 32 +- ...pi-vws-map.dtsi => npcx-espi-vws-map.dtsi} | 4 +- ...-ctrl-map.dtsi => npcx-lvol-ctrl-map.dtsi} | 5 +- ...s-int-map.dtsi => npcx-miwus-int-map.dtsi} | 17 +- ...s-wui-map.dtsi => npcx-miwus-wui-map.dtsi} | 8 +- ...l-ctrl-map.dtsi => npcx-psl-ctrl-map.dtsi} | 0 .../nuvoton/npcx/npcx7/npcx7-alts-map.dtsi | 52 ++ .../npcx/npcx7/npcx7-espi-vws-map.dtsi | 10 + .../npcx/npcx7/npcx7-lvol-ctrl-map.dtsi | 20 + .../npcx/npcx7/npcx7-miwus-int-map.dtsi | 41 ++ .../npcx/npcx7/npcx7-miwus-wui-map.dtsi | 27 + .../npcx/npcx7/npcx7-psl-ctrl-map.dtsi | 10 + dts/arm/nuvoton/npcx7.dtsi | 583 +--------------- 14 files changed, 807 insertions(+), 630 deletions(-) create mode 100644 dts/arm/nuvoton/npcx.dtsi rename dts/arm/nuvoton/npcx/{npcx7-alts-map.dtsi => npcx-alts-map.dtsi} (90%) rename dts/arm/nuvoton/npcx/{npcx7-espi-vws-map.dtsi => npcx-espi-vws-map.dtsi} (97%) rename dts/arm/nuvoton/npcx/{npcx7-lvol-ctrl-map.dtsi => npcx-lvol-ctrl-map.dtsi} (95%) rename dts/arm/nuvoton/npcx/{npcx7-miwus-int-map.dtsi => npcx-miwus-int-map.dtsi} (83%) rename dts/arm/nuvoton/npcx/{npcx7-miwus-wui-map.dtsi => npcx-miwus-wui-map.dtsi} (98%) rename dts/arm/nuvoton/npcx/{npcx7-psl-ctrl-map.dtsi => npcx-psl-ctrl-map.dtsi} (100%) create mode 100644 dts/arm/nuvoton/npcx/npcx7/npcx7-alts-map.dtsi create mode 100644 dts/arm/nuvoton/npcx/npcx7/npcx7-espi-vws-map.dtsi create mode 100644 dts/arm/nuvoton/npcx/npcx7/npcx7-lvol-ctrl-map.dtsi create mode 100644 dts/arm/nuvoton/npcx/npcx7/npcx7-miwus-int-map.dtsi create mode 100644 dts/arm/nuvoton/npcx/npcx7/npcx7-miwus-wui-map.dtsi create mode 100644 dts/arm/nuvoton/npcx/npcx7/npcx7-psl-ctrl-map.dtsi diff --git a/dts/arm/nuvoton/npcx.dtsi b/dts/arm/nuvoton/npcx.dtsi new file mode 100644 index 00000000000..2af8d58ad0e --- /dev/null +++ b/dts/arm/nuvoton/npcx.dtsi @@ -0,0 +1,628 @@ +/* + * Copyright (c) 2021 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/* Macros for device tree declarations of npcx soc family */ +#include +#include +#include +#include +#include +#include + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-m4f"; + reg = <0>; + }; + }; + + def-io-conf-list { + compatible = "nuvoton,npcx-pinctrl-def"; + /* Change default functional pads to GPIOs + * no_spip - PIN95.97.A1.A3 + * no_fpip - PIN96.A0.A2.A4 - Internal flash only + * no_pwrgd - PIN72 + * no_lpc_espi - PIN46.47.51.52.53.54.55.57 + * no_peci_en - PIN81 + * npsl_in1_sl - PIND2 + * npsl_in2_sl - PIN00 + * no_ksi0-7 - PIN31.30.27.26.25.24.23.22 + * no_ks000-17 - PIN21.20.17.16.15.14.13.12.11.10.07.06.05.04. + * 82.83.03.B1 + */ + pinctrl-0 = <>; + }; + + def-lvol-io-list { + compatible = "nuvoton,npcx-lvolctrl-def"; + /* Put low-voltage io pads into "lvol-io-pads" property if the + * detection level of them is 1.8V, For example, if the bus + * voltage of i2c1_0 port is 1.8V, this property should be: + * lvol-io-pads = <&lvol_io90 &lvol_io87>; + */ + lvol-io-pads = <>; + }; + + vsby-psl-in-list { + compatible = "nuvoton,npcx-pslctrl-def"; + /* Put Power Switch Logic (PSL) input pads which detect the + * wake-up events and turn on core power supply (VCC1) from + * standby power state (ultra-low-power mode) into "psl-in-pads" + * property. For example, if PSL input 1 that is plan to detect + * a 'falling edge' event, this property should be: + * psl-in-pads = <&psl_in1>; + * And the flag property in psl_in1 should change to + * flag = ; + */ + psl-in-pads = <>; + }; + + soc { + compatible = "syscon"; + + pcc: clock-controller@4000d000 { + compatible = "nuvoton,npcx-pcc"; + /* Cells for bus type, clock control reg and bit */ + #clock-cells = <3>; + /* First reg region is Power Management Controller */ + /* Second reg region is Core Domain Clock Generator */ + reg = <0x4000d000 0x2000 + 0x400b5000 0x2000>; + reg-names = "pmc", "cdcg"; + label = "PMC_CDCG"; + }; + + scfg: scfg@400c3000 { + compatible = "nuvoton,npcx-scfg"; + /* First reg region is System Configuration Device */ + /* Second reg region is System Glue Device */ + reg = <0x400c3000 0x70 + 0x400a5000 0x2000>; + reg-names = "scfg", "glue"; + #alt-cells = <3>; + #lvol-cells = <4>; + label = "SCFG"; + }; + + miwu0: miwu@400bb000 { + compatible = "nuvoton,npcx-miwu"; + reg = <0x400bb000 0x2000>; + index = <0>; + #miwu-cells = <2>; + label="MIWU_0"; + }; + + miwu1: miwu@400bd000 { + compatible = "nuvoton,npcx-miwu"; + reg = <0x400bd000 0x2000>; + index = <1>; + #miwu-cells = <2>; + label="MIWU_1"; + }; + + miwu2: miwu@400bf000 { + compatible = "nuvoton,npcx-miwu"; + reg = <0x400bf000 0x2000>; + index = <2>; + #miwu-cells = <2>; + label="MIWU_2"; + }; + + gpio0: gpio@40081000 { + compatible = "nuvoton,npcx-gpio"; + reg = <0x40081000 0x2000>; + gpio-controller; + index = <0x0>; + #gpio-cells=<2>; + label="GPIO_0"; + }; + + gpio1: gpio@40083000 { + compatible = "nuvoton,npcx-gpio"; + reg = <0x40083000 0x2000>; + gpio-controller; + index = <0x1>; + #gpio-cells=<2>; + label="GPIO_1"; + }; + + gpio2: gpio@40085000 { + compatible = "nuvoton,npcx-gpio"; + reg = <0x40085000 0x2000>; + gpio-controller; + index = <0x2>; + #gpio-cells=<2>; + label="GPIO_2"; + }; + + gpio3: gpio@40087000 { + compatible = "nuvoton,npcx-gpio"; + reg = <0x40087000 0x2000>; + gpio-controller; + index = <0x3>; + #gpio-cells=<2>; + label="GPIO_3"; + }; + + gpio4: gpio@40089000 { + compatible = "nuvoton,npcx-gpio"; + reg = <0x40089000 0x2000>; + gpio-controller; + index = <0x4>; + #gpio-cells=<2>; + label="GPIO_4"; + }; + + gpio5: gpio@4008b000 { + compatible = "nuvoton,npcx-gpio"; + reg = <0x4008b000 0x2000>; + gpio-controller; + index = <0x5>; + #gpio-cells=<2>; + label="GPIO_5"; + }; + + gpio6: gpio@4008d000 { + compatible = "nuvoton,npcx-gpio"; + reg = <0x4008d000 0x2000>; + gpio-controller; + index = <0x6>; + #gpio-cells=<2>; + label="GPIO_6"; + }; + + gpio7: gpio@4008f000 { + compatible = "nuvoton,npcx-gpio"; + reg = <0x4008f000 0x2000>; + gpio-controller; + index = <0x7>; + #gpio-cells=<2>; + label="GPIO_7"; + }; + + gpio8: gpio@40091000 { + compatible = "nuvoton,npcx-gpio"; + reg = <0x40091000 0x2000>; + gpio-controller; + index = <0x8>; + #gpio-cells=<2>; + label="GPIO_8"; + }; + + gpio9: gpio@40093000 { + compatible = "nuvoton,npcx-gpio"; + reg = <0x40093000 0x2000>; + gpio-controller; + index = <0x9>; + #gpio-cells=<2>; + label="GPIO_9"; + }; + + gpioa: gpio@40095000 { + compatible = "nuvoton,npcx-gpio"; + reg = <0x40095000 0x2000>; + gpio-controller; + index = <0xA>; + #gpio-cells=<2>; + label="GPIO_A"; + }; + + gpiob: gpio@40097000 { + compatible = "nuvoton,npcx-gpio"; + reg = <0x40097000 0x2000>; + gpio-controller; + index = <0xB>; + #gpio-cells=<2>; + label="GPIO_B"; + }; + + gpioc: gpio@40099000 { + compatible = "nuvoton,npcx-gpio"; + reg = <0x40099000 0x2000>; + gpio-controller; + index = <0xC>; + #gpio-cells=<2>; + label="GPIO_C"; + }; + + gpiod: gpio@4009b000 { + compatible = "nuvoton,npcx-gpio"; + reg = <0x4009b000 0x2000>; + gpio-controller; + index = <0xD>; + #gpio-cells=<2>; + label="GPIO_D"; + }; + + gpioe: gpio@4009d000 { + compatible = "nuvoton,npcx-gpio"; + reg = <0x4009d000 0x2000>; + gpio-controller; + index = <0xE>; + #gpio-cells=<2>; + label="GPIO_E"; + }; + + gpiof: gpio@4009f000 { + compatible = "nuvoton,npcx-gpio"; + reg = <0x4009f000 0x2000>; + gpio-controller; + index = <0xF>; + #gpio-cells=<2>; + label="GPIO_F"; + }; + + pwm0: pwm@40080000 { + compatible = "nuvoton,npcx-pwm"; + reg = <0x40080000 0x2000>; + clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 0>; + pinctrl-0 = <&alt4_pwm0_sl>; /* PINC3 */ + #pwm-cells = <2>; + status = "disabled"; + label = "PWM_0"; + }; + + pwm1: pwm@40082000 { + compatible = "nuvoton,npcx-pwm"; + reg = <0x40082000 0x2000>; + clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 1>; + pinctrl-0 = <&alt4_pwm1_sl>; /* PINC2 */ + #pwm-cells = <2>; + status = "disabled"; + label = "PWM_1"; + }; + + pwm2: pwm@40084000 { + compatible = "nuvoton,npcx-pwm"; + reg = <0x40084000 0x2000>; + clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 2>; + pinctrl-0 = <&alt4_pwm2_sl>; /* PINC4 */ + #pwm-cells = <2>; + status = "disabled"; + label = "PWM_2"; + }; + + pwm3: pwm@40086000 { + compatible = "nuvoton,npcx-pwm"; + reg = <0x40086000 0x2000>; + clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 3>; + pinctrl-0 = <&alt4_pwm3_sl>; /* PIN80 */ + #pwm-cells = <2>; + status = "disabled"; + label = "PWM_3"; + }; + + pwm4: pwm@40088000 { + compatible = "nuvoton,npcx-pwm"; + reg = <0x40088000 0x2000>; + clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 4>; + pinctrl-0 = <&alt4_pwm4_sl>; /* PINB6 */ + #pwm-cells = <2>; + status = "disabled"; + label = "PWM_4"; + }; + + pwm5: pwm@4008a000 { + compatible = "nuvoton,npcx-pwm"; + reg = <0x4008a000 0x2000>; + clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 5>; + pinctrl-0 = <&alt4_pwm5_sl>; /* PINB7 */ + #pwm-cells = <2>; + status = "disabled"; + label = "PWM_5"; + }; + + pwm6: pwm@4008c000 { + compatible = "nuvoton,npcx-pwm"; + reg = <0x4008c000 0x2000>; + clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 6>; + pinctrl-0 = <&alt4_pwm6_sl>; /* PINC0 */ + #pwm-cells = <2>; + status = "disabled"; + label = "PWM_6"; + }; + + pwm7: pwm@4008e000 { + compatible = "nuvoton,npcx-pwm"; + reg = <0x4008e000 0x2000>; + clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 7>; + pinctrl-0 = <&alt4_pwm7_sl>; /* PIN60 */ + #pwm-cells = <2>; + status = "disabled"; + label = "PWM_7"; + }; + + adc0: adc@400d1000 { + compatible = "nuvoton,npcx-adc"; + #io-channel-cells = <1>; + reg = <0x400d1000 0x2000>; + interrupts = <10 3>; + clocks = <&pcc NPCX_CLOCK_BUS_APB1 NPCX_PWDWN_CTL4 4>; + status = "disabled"; + label = "ADC_0"; + }; + + twd0: watchdog@400d8000 { + compatible = "nuvoton,npcx-watchdog"; + reg = <0x400d8000 0x2000>; + t0-out = <&wui_t0out>; + label = "TWD_0"; + }; + + espi0: espi@4000a000 { + compatible = "nuvoton,npcx-espi"; + reg = <0x4000a000 0x2000>; + interrupts = <18 3>; /* Interrupt for eSPI Bus */ + + /* clocks for eSPI modules */ + clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL6 7>; + /* PIN46.47.51.52.53.54.55.57 */ + pinctrl-0 = <&alt1_no_lpc_espi>; + /* WUI maps for eSPI signals */ + espi-rst-wui = <&wui_espi_rst>; + label = "ESPI_0"; + + #address-cells = <1>; + #size-cells = <0>; + #vw-cells = <3>; + status = "disabled"; + }; + + host_sub: lpc@400c1000 { + compatible = "nuvoton,npcx-host-sub"; + /* host sub-module register address & size */ + reg = <0x400c1000 0x2000 + 0x40010000 0x2000 + 0x4000e000 0x2000 + 0x400c7000 0x2000 + 0x400c9000 0x2000 + 0x400cb000 0x2000>; + reg-names = "mswc", "shm", "c2h", "kbc", "pm_acpi", + "pm_hcmd"; + + /* host sub-module IRQ and priority */ + interrupts = <25 3>, /* KBC Input-Buf-Full (IBF) */ + <56 3>, /* KBC Output-Buf-Empty (OBE) */ + <26 3>, /* PMCH Input-Buf-Full (IBF) */ + <3 3>, /* PMCH Output-Buf-Empty (OBE) */ + <6 3>; /* Port80 FIFO Not Empty */ + interrupt-names = "kbc_ibf", "kbc_obe", "pmch_ibf", + "pmch_obe", "p80_fifo"; + + /* WUI map for accessing host sub-modules */ + host-acc-wui = <&wui_host_acc>; + + /* clocks for host sub-modules */ + clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 3>, + <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 4>, + <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 5>, + <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 6>, + <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 7>; + label = "HOST_SUBS"; + }; + + host_uart: io_host_uart { + compatible = "nuvoton,npcx-host-uart"; + /* Host serial port pinmux PIN75 86 36 33 42 C7 B3 B2 */ + pinctrl-0 = <&altb_rxd_sl &altb_txd_sl + &altb_rts_sl &altb_cts_sl + &altb_ri_sl &altb_dtr_bout_sl + &altb_dcd_sl &altb_dsr_sl>; + label = "HOST_UART_IO"; + status = "disabled"; + }; + + /* I2c Controllers - Do not use them as i2c node directly */ + i2c_ctrl0: i2c@40009000 { + compatible = "nuvoton,npcx-i2c-ctrl"; + reg = <0x40009000 0x1000>; + interrupts = <13 3>; + clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL3 0>; + label = "I2CCTRL_0"; + }; + + i2c_ctrl1: i2c@4000b000 { + compatible = "nuvoton,npcx-i2c-ctrl"; + reg = <0x4000b000 0x1000>; + interrupts = <14 3>; + clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL3 1>; + label = "I2CCTRL_1"; + }; + + i2c_ctrl2: i2c@400c0000 { + compatible = "nuvoton,npcx-i2c-ctrl"; + reg = <0x400c0000 0x1000>; + interrupts = <36 3>; + clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL3 2>; + label = "I2CCTRL_2"; + }; + + i2c_ctrl3: i2c@400c2000 { + compatible = "nuvoton,npcx-i2c-ctrl"; + reg = <0x400c2000 0x1000>; + interrupts = <37 3>; + clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL3 3>; + label = "I2CCTRL_3"; + }; + + i2c_ctrl4: i2c@40008000 { + compatible = "nuvoton,npcx-i2c-ctrl"; + reg = <0x40008000 0x1000>; + interrupts = <19 3>; + clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL3 4>; + label = "I2CCTRL_4"; + }; + + i2c_ctrl5: i2c@40017000 { + compatible = "nuvoton,npcx-i2c-ctrl"; + reg = <0x40017000 0x1000>; + interrupts = <20 3>; + clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL7 0>; + label = "I2CCTRL_5"; + }; + + i2c_ctrl6: i2c@40018000 { + compatible = "nuvoton,npcx-i2c-ctrl"; + reg = <0x40018000 0x1000>; + interrupts = <16 3>; + clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL7 1>; + label = "I2CCTRL_6"; + }; + + i2c_ctrl7: i2c@40019000 { + compatible = "nuvoton,npcx-i2c-ctrl"; + reg = <0x40019000 0x1000>; + interrupts = <8 3>; + clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL7 2>; + label = "I2CCTRL_7"; + }; + + /* I2c Ports - Please use them as i2c node */ + i2c0_0: io_i2c_ctrl0_port0 { + compatible = "nuvoton,npcx-i2c-port"; + #address-cells = <1>; + #size-cells = <0>; + port = <0x00>; + controller = <&i2c_ctrl0>; + pinctrl-0 = <&alt2_i2c0_0_sl>; /* PINB5.B4 */ + label = "I2C_0_PORT_0"; + status = "disabled"; + }; + + i2c1_0: io_i2c_ctrl1_port0 { + compatible = "nuvoton,npcx-i2c-port"; + #address-cells = <1>; + #size-cells = <0>; + port = <0x10>; + controller = <&i2c_ctrl1>; + pinctrl-0 = <&alt2_i2c1_0_sl>; /* PIN90.87 */ + label = "I2C_1_PORT_0"; + status = "disabled"; + }; + + i2c2_0: io_i2c_ctrl2_port0 { + compatible = "nuvoton,npcx-i2c-port"; + #address-cells = <1>; + #size-cells = <0>; + port = <0x20>; + controller = <&i2c_ctrl2>; + pinctrl-0 = <&alt2_i2c2_0_sl>; /* PIN92.91 */ + label = "I2C_2_PORT_0"; + status = "disabled"; + }; + + i2c3_0: io_i2c_ctrl3_port0 { + compatible = "nuvoton,npcx-i2c-port"; + #address-cells = <1>; + #size-cells = <0>; + port = <0x30>; + controller = <&i2c_ctrl3>; + pinctrl-0 = <&alt2_i2c3_0_sl>; /* PIND1.D0 */ + label = "I2C_3_PORT_0"; + status = "disabled"; + }; + + i2c4_1: io_i2c_ctrl4_port1 { + compatible = "nuvoton,npcx-i2c-port"; + #address-cells = <1>; + #size-cells = <0>; + port = <0x41>; + controller = <&i2c_ctrl4>; + pinctrl-0 = <&alt6_i2c4_1_sl>; /* PINF3.F2 */ + label = "I2C_4_PORT_1"; + status = "disabled"; + }; + + i2c5_0: io_i2c_ctrl5_port0 { + compatible = "nuvoton,npcx-i2c-port"; + #address-cells = <1>; + #size-cells = <0>; + port = <0x50>; + controller = <&i2c_ctrl5>; + pinctrl-0 = <&alt2_i2c5_0_sl>; /* PIN33.36 */ + label = "I2C_5_PORT_0"; + status = "disabled"; + }; + + i2c5_1: io_i2c_ctrl5_port1 { + compatible = "nuvoton,npcx-i2c-port"; + #address-cells = <1>; + #size-cells = <0>; + port = <0x51>; + controller = <&i2c_ctrl5>; + pinctrl-0 = <&alt6_i2c5_1_sl>; /* PINF5.F4 */ + label = "I2C_5_PORT_1"; + status = "disabled"; + }; + + i2c6_0: io_i2c_ctrl6_port0 { + compatible = "nuvoton,npcx-i2c-port"; + #address-cells = <1>; + #size-cells = <0>; + port = <0x60>; + controller = <&i2c_ctrl6>; + pinctrl-0 = <&alt2_i2c6_0_sl>; /* PINC2.C1 */ + label = "I2C_6_PORT_0"; + status = "disabled"; + }; + + i2c6_1: io_i2c_ctrl6_port1 { + compatible = "nuvoton,npcx-i2c-port"; + #address-cells = <1>; + #size-cells = <0>; + port = <0x61>; + controller = <&i2c_ctrl6>; + pinctrl-0 = <&alt6_i2c6_1_sl>; /* PINE4.E3 */ + label = "I2C_6_PORT_1"; + status = "disabled"; + }; + + i2c7_0: io_i2c_ctrl7_port0 { + compatible = "nuvoton,npcx-i2c-port"; + #address-cells = <1>; + #size-cells = <0>; + port = <0x70>; + controller = <&i2c_ctrl7>; + pinctrl-0 = <&alt2_i2c7_0_sl>; /* PINB3.B2 */ + label = "I2C_7_PORT_0"; + status = "disabled"; + }; + + tach1: tach@400e1000 { + compatible = "nuvoton,npcx-tach"; + reg = <0x400e1000 0x2000>; + clocks = <&pcc NPCX_CLOCK_BUS_LFCLK NPCX_PWDWN_CTL1 5>; + label = "TACH_1"; + status = "disabled"; + }; + + tach2: tach@400e3000 { + compatible = "nuvoton,npcx-tach"; + reg = <0x400e3000 0x2000>; + clocks = <&pcc NPCX_CLOCK_BUS_LFCLK NPCX_PWDWN_CTL1 6>; + label = "TACH_2"; + status = "disabled"; + }; + + psl_out: psl-out { + compatible = "nuvoton,npcx-psl-out"; + controller = <&gpio8>; + pin = <5>; + label = "PSL_OUT"; + }; + }; +}; + +&nvic { + arm,num-irq-priority-bits = <3>; +}; diff --git a/dts/arm/nuvoton/npcx/npcx7-alts-map.dtsi b/dts/arm/nuvoton/npcx/npcx-alts-map.dtsi similarity index 90% rename from dts/arm/nuvoton/npcx/npcx7-alts-map.dtsi rename to dts/arm/nuvoton/npcx/npcx-alts-map.dtsi index 071db727830..51569dc786d 100644 --- a/dts/arm/nuvoton/npcx/npcx7-alts-map.dtsi +++ b/dts/arm/nuvoton/npcx/npcx-alts-map.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020 Nuvoton Technology Corporation. + * Copyright (c) 2021 Nuvoton Technology Corporation. * * SPDX-License-Identifier: Apache-2.0 */ @@ -25,9 +25,6 @@ alt1_kbrst_sl: alt10 { alts = <&scfg 0x01 0x0 0>; }; - alt1_a20m_sl: alt11 { - alts = <&scfg 0x01 0x1 0>; - }; alt1_smi_sl: alt12 { alts = <&scfg 0x01 0x2 0>; }; @@ -120,12 +117,6 @@ alt5_trace_en: alt50 { alts = <&scfg 0x05 0x0 0>; }; - alt5_njen1_en: alt51-inv { - alts = <&scfg 0x05 0x1 1>; - }; - alt5_njen0_en: alt52-inv { - alts = <&scfg 0x05 0x2 1>; - }; alt5_strace_en: alt54 { alts = <&scfg 0x05 0x4 0>; }; @@ -244,21 +235,12 @@ alta_32k_out_sl: alta2 { alts = <&scfg 0x0A 0x2 0>; }; - alta_32kclkin_sl: alta3 { - alts = <&scfg 0x0A 0x3 0>; - }; alta_no_vcc1_rst: alta4-inv { alts = <&scfg 0x0A 0x4 1>; }; - alta_uart2_sl: alta5 { - alts = <&scfg 0x0A 0x5 0>; - }; alta_no_peci_en: alta6-inv { alts = <&scfg 0x0A 0x6 1>; }; - alta_uart1_sl1: alta7 { - alts = <&scfg 0x0A 0x7 0>; - }; /* SCFG DEVALT B */ altb_rxd_sl: altb0 { @@ -287,9 +269,6 @@ }; /* SCFG DEVALT C */ - altc_uart1_sl2: altc0 { - alts = <&scfg 0x0C 0x0 0>; - }; altc_shi_sl: altc1 { alts = <&scfg 0x0C 0x1 0>; }; @@ -336,15 +315,6 @@ }; /* SCFG DEVALT E */ - alte_wov_sl: alte0 { - alts = <&scfg 0x0E 0x0 0>; - }; - alte_i2s_sl: alte1 { - alts = <&scfg 0x0E 0x1 0>; - }; - alte_dmclk_fast: alte2 { - alts = <&scfg 0x0E 0x2 0>; - }; /* SCFG DEVALT F */ altf_adc5_sl: altf0 { diff --git a/dts/arm/nuvoton/npcx/npcx7-espi-vws-map.dtsi b/dts/arm/nuvoton/npcx/npcx-espi-vws-map.dtsi similarity index 97% rename from dts/arm/nuvoton/npcx/npcx7-espi-vws-map.dtsi rename to dts/arm/nuvoton/npcx/npcx-espi-vws-map.dtsi index ae63de6fa32..f969e726209 100644 --- a/dts/arm/nuvoton/npcx/npcx7-espi-vws-map.dtsi +++ b/dts/arm/nuvoton/npcx/npcx-espi-vws-map.dtsi @@ -1,9 +1,11 @@ /* - * Copyright (c) 2020 Nuvoton Technology Corporation. + * Copyright (c) 2021 Nuvoton Technology Corporation. * * SPDX-License-Identifier: Apache-2.0 */ +#include + /* * Nuvoton NPCX7 eSPI Virtual Wires Mapping Table * |--------------------------------------------------------------------------| diff --git a/dts/arm/nuvoton/npcx/npcx7-lvol-ctrl-map.dtsi b/dts/arm/nuvoton/npcx/npcx-lvol-ctrl-map.dtsi similarity index 95% rename from dts/arm/nuvoton/npcx/npcx7-lvol-ctrl-map.dtsi rename to dts/arm/nuvoton/npcx/npcx-lvol-ctrl-map.dtsi index 4c513e5d754..e716281e6b5 100644 --- a/dts/arm/nuvoton/npcx/npcx7-lvol-ctrl-map.dtsi +++ b/dts/arm/nuvoton/npcx/npcx-lvol-ctrl-map.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020 Nuvoton Technology Corporation. + * Copyright (c) 2021 Nuvoton Technology Corporation. * * SPDX-License-Identifier: Apache-2.0 */ @@ -95,9 +95,6 @@ }; /* Low-Voltage IO Control 4 */ - lvol_io86: lvol40 { - lvols = <&scfg 0x08 6 4 0>; - }; lvol_ioc2: lvol41 { lvols = <&scfg 0x0c 2 4 1>; }; diff --git a/dts/arm/nuvoton/npcx/npcx7-miwus-int-map.dtsi b/dts/arm/nuvoton/npcx/npcx-miwus-int-map.dtsi similarity index 83% rename from dts/arm/nuvoton/npcx/npcx7-miwus-int-map.dtsi rename to dts/arm/nuvoton/npcx/npcx-miwus-int-map.dtsi index 2108d6186b1..9b3cf781d71 100644 --- a/dts/arm/nuvoton/npcx/npcx7-miwus-int-map.dtsi +++ b/dts/arm/nuvoton/npcx/npcx-miwus-int-map.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020 Nuvoton Technology Corporation. + * Copyright (c) 2021 Nuvoton Technology Corporation. * * SPDX-License-Identifier: Apache-2.0 */ @@ -11,11 +11,6 @@ compatible = "nuvoton,npcx-miwu-int-map"; parent = <&miwu0>; - group_ad0: group-ad0-map { - irq = <7>; - irq-prio = <2>; - group-mask = <0x09>; - }; group_b0: group-b0-map { irq = <31>; irq-prio = <2>; @@ -26,11 +21,6 @@ irq-prio = <2>; group-mask = <0x04>; }; - group_efgh0: group-efgh0-map { - irq = <11>; - irq-prio = <2>; - group-mask = <0xF0>; - }; }; map_miwu1_groups: map-miwu1-groups { @@ -103,11 +93,6 @@ irq-prio = <2>; group-mask = <0x08>; }; - group_fg2: group-fg2-map { - irq = <59>; - irq-prio = <2>; - group-mask = <0x60>; - }; }; }; }; diff --git a/dts/arm/nuvoton/npcx/npcx7-miwus-wui-map.dtsi b/dts/arm/nuvoton/npcx/npcx-miwus-wui-map.dtsi similarity index 98% rename from dts/arm/nuvoton/npcx/npcx7-miwus-wui-map.dtsi rename to dts/arm/nuvoton/npcx/npcx-miwus-wui-map.dtsi index 26b1f968c92..48723fdcd44 100644 --- a/dts/arm/nuvoton/npcx/npcx7-miwus-wui-map.dtsi +++ b/dts/arm/nuvoton/npcx/npcx-miwus-wui-map.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020 Nuvoton Technology Corporation. + * Copyright (c) 2021 Nuvoton Technology Corporation. * * SPDX-License-Identifier: Apache-2.0 */ @@ -23,9 +23,6 @@ wui_io83: wui0-1-3 { miwus = <&miwu0 0 3>; /* GPIO83 */ }; - wui_io86: wui0-1-6 { - miwus = <&miwu0 0 6>; /* GPIO86 */ - }; wui_cr_sin2: wui0-1-6-2 { miwus = <&miwu0 0 6>; /* CR_SIN2 */ }; @@ -182,9 +179,6 @@ wui_iod5: wui0-7-5 { miwus = <&miwu0 6 5>; /* GPIOD5 */ }; - wui_iod7: wui0-7-6 { - miwus = <&miwu0 6 6>; /* GPIOD7 */ - }; wui_ioe0: wui0-7-7 { miwus = <&miwu0 6 7>; /* GPIOE0 */ }; diff --git a/dts/arm/nuvoton/npcx/npcx7-psl-ctrl-map.dtsi b/dts/arm/nuvoton/npcx/npcx-psl-ctrl-map.dtsi similarity index 100% rename from dts/arm/nuvoton/npcx/npcx7-psl-ctrl-map.dtsi rename to dts/arm/nuvoton/npcx/npcx-psl-ctrl-map.dtsi diff --git a/dts/arm/nuvoton/npcx/npcx7/npcx7-alts-map.dtsi b/dts/arm/nuvoton/npcx/npcx7/npcx7-alts-map.dtsi new file mode 100644 index 00000000000..f28f6fab9d4 --- /dev/null +++ b/dts/arm/nuvoton/npcx/npcx7/npcx7-alts-map.dtsi @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2020 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Common pin-mux configurations in npcx family */ +#include + +/* Specific pin-mux configurations in npcx7 series */ +/ { + npcx-alts-map { + compatible = "nuvoton,npcx-pinctrl-conf"; + + /* SCFG DEVALT 5 */ + alt5_njen1_en: alt51-inv { + alts = <&scfg 0x05 0x1 1>; + }; + alt5_njen0_en: alt52-inv { + alts = <&scfg 0x05 0x2 1>; + }; + + /* SCFG DEVALT 1 */ + alt1_a20m_sl: alt11 { + alts = <&scfg 0x01 0x1 0>; + }; + + /* SCFG DEVALT A */ + alta_uart2_sl: alta5 { + alts = <&scfg 0x0A 0x5 0>; + }; + alta_uart1_sl1: alta7 { + alts = <&scfg 0x0A 0x7 0>; + }; + + /* SCFG DEVALT C */ + altc_uart1_sl2: altc0 { + alts = <&scfg 0x0C 0x0 0>; + }; + + /* SCFG DEVALT E */ + alte_wov_sl: alte0 { + alts = <&scfg 0x0E 0x0 0>; + }; + alte_i2s_sl: alte1 { + alts = <&scfg 0x0E 0x1 0>; + }; + alte_dmclk_fast: alte2 { + alts = <&scfg 0x0E 0x2 0>; + }; + }; +}; diff --git a/dts/arm/nuvoton/npcx/npcx7/npcx7-espi-vws-map.dtsi b/dts/arm/nuvoton/npcx/npcx7/npcx7-espi-vws-map.dtsi new file mode 100644 index 00000000000..d9d542bb77f --- /dev/null +++ b/dts/arm/nuvoton/npcx/npcx7/npcx7-espi-vws-map.dtsi @@ -0,0 +1,10 @@ +/* + * Copyright (c) 2020 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Common eSPI Virtual Wire (VW) mapping configurations in npcx family */ +#include + +/* Specific eSPI Virtual Wire (VW) mapping configurations in npcx7 series */ diff --git a/dts/arm/nuvoton/npcx/npcx7/npcx7-lvol-ctrl-map.dtsi b/dts/arm/nuvoton/npcx/npcx7/npcx7-lvol-ctrl-map.dtsi new file mode 100644 index 00000000000..2f972e11da5 --- /dev/null +++ b/dts/arm/nuvoton/npcx/npcx7/npcx7-lvol-ctrl-map.dtsi @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2021 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Common Low-Voltage level configurations in npcx family */ +#include + +/* Specific Low-Voltage level configurations in npcx7 series */ +/ { + def-lvol-conf-list { + compatible = "nuvoton,npcx-lvolctrl-conf"; + + /* Low-Voltage IO Control 4 */ + lvol_io86: lvol40 { + lvols = <&scfg 0x08 6 4 0>; + }; + }; +}; diff --git a/dts/arm/nuvoton/npcx/npcx7/npcx7-miwus-int-map.dtsi b/dts/arm/nuvoton/npcx/npcx7/npcx7-miwus-int-map.dtsi new file mode 100644 index 00000000000..fbf1f13694e --- /dev/null +++ b/dts/arm/nuvoton/npcx/npcx7/npcx7-miwus-int-map.dtsi @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2020 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Common MIWU group-interrupt mapping configurations in npcx family */ +#include + +/* Specific MIWU group-interrupt mapping configurations in npcx7 series */ +/ { + /* Mapping between MIWU group and interrupts */ + npcx-miwus-int-map { + map_miwu0_groups: map-miwu0-groups { + compatible = "nuvoton,npcx-miwu-int-map"; + parent = <&miwu0>; + + group_ad0: group-ad0-map { + irq = <7>; + irq-prio = <2>; + group-mask = <0x09>; + }; + group_efgh0: group-efgh0-map { + irq = <11>; + irq-prio = <2>; + group-mask = <0xF0>; + }; + }; + + map_miwu2_groups: map-miwu2-groups { + compatible = "nuvoton,npcx-miwu-int-map"; + parent = <&miwu2>; + + group_fg2: group-fg2-map { + irq = <59>; + irq-prio = <2>; + group-mask = <0x60>; + }; + }; + }; +}; diff --git a/dts/arm/nuvoton/npcx/npcx7/npcx7-miwus-wui-map.dtsi b/dts/arm/nuvoton/npcx/npcx7/npcx7-miwus-wui-map.dtsi new file mode 100644 index 00000000000..ccfda809b2e --- /dev/null +++ b/dts/arm/nuvoton/npcx/npcx7/npcx7-miwus-wui-map.dtsi @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2020 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Common Wake-Up Unit Input (WUI) mapping configurations in npcx family */ +#include + +/* Specific Wake-Up Unit Input (WUI) mapping configurations in npcx7 series */ +/ { + /* Mapping between MIWU wui bits and source device */ + npcx-miwus-wui-map { + compatible = "nuvoton,npcx-miwu-wui-map"; + + /* MIWU table 0 */ + /* MIWU group A */ + wui_io86: wui0-1-6 { + miwus = <&miwu0 0 6>; /* GPIO86 */ + }; + + /* MIWU group G */ + wui_iod7: wui0-7-6 { + miwus = <&miwu0 6 6>; /* GPIOD7 */ + }; + }; +}; diff --git a/dts/arm/nuvoton/npcx/npcx7/npcx7-psl-ctrl-map.dtsi b/dts/arm/nuvoton/npcx/npcx7/npcx7-psl-ctrl-map.dtsi new file mode 100644 index 00000000000..cd9a21e192a --- /dev/null +++ b/dts/arm/nuvoton/npcx/npcx7/npcx7-psl-ctrl-map.dtsi @@ -0,0 +1,10 @@ +/* + * Copyright (c) 2021 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Common Power Switch Logic (PSL) pads configurations in npcx family */ +#include + +/* Specific Power Switch Logic (PSL) pads configurations in npcx7 series */ diff --git a/dts/arm/nuvoton/npcx7.dtsi b/dts/arm/nuvoton/npcx7.dtsi index bc78c754f05..d8e1d01482b 100644 --- a/dts/arm/nuvoton/npcx7.dtsi +++ b/dts/arm/nuvoton/npcx7.dtsi @@ -4,55 +4,24 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include -/* Macros for device tree declarations */ -#include -#include -#include -#include -#include -#include -#include - /* NPCX7 series pinmux mapping table */ -#include "npcx/npcx7-alts-map.dtsi" +#include "npcx/npcx7/npcx7-alts-map.dtsi" /* NPCX7 series mapping table between MIWU wui bits and source device */ -#include "npcx/npcx7-miwus-wui-map.dtsi" +#include "npcx/npcx7/npcx7-miwus-wui-map.dtsi" /* NPCX7 series mapping table between MIWU groups and interrupts */ -#include "npcx/npcx7-miwus-int-map.dtsi" +#include "npcx/npcx7/npcx7-miwus-int-map.dtsi" /* NPCX7 series eSPI VW mapping table */ -#include "npcx/npcx7-espi-vws-map.dtsi" +#include "npcx/npcx7/npcx7-espi-vws-map.dtsi" /* NPCX7 series low-voltage io controls mapping table */ -#include "npcx/npcx7-lvol-ctrl-map.dtsi" +#include "npcx/npcx7/npcx7-lvol-ctrl-map.dtsi" /* NPCX7 series power-switch-logic (PSL) io controls mapping table */ -#include "npcx/npcx7-psl-ctrl-map.dtsi" +#include "npcx/npcx7/npcx7-psl-ctrl-map.dtsi" + +/* Device tree declarations of npcx soc family */ +#include "npcx.dtsi" / { - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-m4f"; - reg = <0>; - }; - }; - def-io-conf-list { - compatible = "nuvoton,npcx-pinctrl-def"; - /* Change default functional pads to GPIOs - * no_spip - PIN95.97.A1.A3 - * no_fpip - PIN96.A0.A2.A4 - Internal flash only - * no_pwrgd - PIN72 - * no_lpc_espi - PIN46.47.51.52.53.54.55.57 - * no_peci_en - PIN81 - * npsl_in1_sl - PIND2 - * npsl_in2_sl - PIN00 - * no_ksi0-7 - PIN31.30.27.26.25.24.23.22 - * no_ks000-17 - PIN21.20.17.16.15.14.13.12.11.10.07.06.05.04. - * 82.83.03.B1 - */ pinctrl-0 = <&alt0_gpio_no_spip &alt0_gpio_no_fpip &alt1_no_pwrgd @@ -88,33 +57,8 @@ &alta_no_kso17_sl>; }; - def-lvol-io-list { - compatible = "nuvoton,npcx-lvolctrl-def"; - /* Put low-voltage io pads into "lvol-io-pads" property if the - * detection level of them is 1.8V, For example, if the bus - * voltage of i2c1_0 port is 1.8V, this property should be: - * lvol-io-pads = <&lvol_io90 &lvol_io87>; - */ - lvol-io-pads = <>; - }; - - vsby-psl-in-list { - compatible = "nuvoton,npcx-pslctrl-def"; - /* Put Power Switch Logic (PSL) input pads which detect the - * wake-up events and turn on core power supply (VCC1) from - * standby power state (ultra-low-power mode) into "psl-in-pads" - * property. For example, if PSL input 1 that is plan to detect - * a 'falling edge' event, this property should be: - * psl-in-pads = <&psl_in1>; - * And the flag property in psl_in1 should change to - * flag = ; - */ - psl-in-pads = <>; - }; - soc { - compatible = "syscon"; - + /* Specific soc devices in npcx7 series */ itims: timer@400bc000 { compatible = "nuvoton,npcx-itim-timer"; reg = <0x400bc000 0x2000 @@ -126,30 +70,6 @@ label = "ITIM"; }; - pcc: clock-controller@4000d000 { - compatible = "nuvoton,npcx-pcc"; - /* Cells for bus type, clock control reg and bit */ - #clock-cells = <3>; - /* First reg region is Power Management Controller */ - /* Second reg region is Core Domain Clock Generator */ - reg = <0x4000d000 0x2000 - 0x400b5000 0x2000>; - reg-names = "pmc", "cdcg"; - label = "PMC_CDCG"; - }; - - scfg: scfg@400c3000 { - compatible = "nuvoton,npcx-scfg"; - /* First reg region is System Configuration Device */ - /* Second reg region is System Glue Device */ - reg = <0x400c3000 0x70 - 0x400a5000 0x2000>; - reg-names = "scfg", "glue"; - #alt-cells = <3>; - #lvol-cells = <4>; - label = "SCFG"; - }; - uart1: serial@400c4000 { compatible = "nuvoton,npcx-uart"; reg = <0x400C4000 0x2000>; @@ -172,292 +92,89 @@ label = "UART_2"; }; - miwu0: miwu@400bb000 { - compatible = "nuvoton,npcx-miwu"; - reg = <0x400bb000 0x2000>; - index = <0>; - #miwu-cells = <2>; - label="MIWU_0"; - }; - - miwu1: miwu@400bd000 { - compatible = "nuvoton,npcx-miwu"; - reg = <0x400bd000 0x2000>; - index = <1>; - #miwu-cells = <2>; - label="MIWU_1"; - }; - - miwu2: miwu@400bf000 { - compatible = "nuvoton,npcx-miwu"; - reg = <0x400bf000 0x2000>; - index = <2>; - #miwu-cells = <2>; - label="MIWU_2"; - }; - + /* Wake-up input source mapping for GPIOs in npcx7 series */ gpio0: gpio@40081000 { - compatible = "nuvoton,npcx-gpio"; - reg = <0x40081000 0x2000>; - gpio-controller; - index = <0x0>; wui-maps = <&wui_io00 &wui_io01 &wui_io02 &wui_io03 &wui_io04 &wui_io05 &wui_io06 &wui_io07>; - #gpio-cells=<2>; - label="GPIO_0"; }; gpio1: gpio@40083000 { - compatible = "nuvoton,npcx-gpio"; - reg = <0x40083000 0x2000>; - gpio-controller; - index = <0x1>; wui-maps = <&wui_io10 &wui_io11 &wui_none &wui_none &wui_io14 &wui_io15 &wui_io16 &wui_io17>; - #gpio-cells=<2>; - label="GPIO_1"; }; gpio2: gpio@40085000 { - compatible = "nuvoton,npcx-gpio"; - reg = <0x40085000 0x2000>; - gpio-controller; - index = <0x2>; wui-maps = <&wui_io20 &wui_io21 &wui_io22 &wui_io23 &wui_io24 &wui_io25 &wui_io26 &wui_io27>; - #gpio-cells=<2>; - label="GPIO_2"; }; gpio3: gpio@40087000 { - compatible = "nuvoton,npcx-gpio"; - reg = <0x40087000 0x2000>; - gpio-controller; - index = <0x3>; wui-maps = <&wui_io30 &wui_io31 &wui_none &wui_io33 &wui_io34 &wui_none &wui_io36 &wui_io37>; - #gpio-cells=<2>; - label="GPIO_3"; }; gpio4: gpio@40089000 { - compatible = "nuvoton,npcx-gpio"; - reg = <0x40089000 0x2000>; - gpio-controller; - index = <0x4>; wui-maps = <&wui_io40 &wui_io41 &wui_io42 &wui_io43 &wui_io44 &wui_io45 &wui_io46 &wui_io47>; - #gpio-cells=<2>; - label="GPIO_4"; }; gpio5: gpio@4008b000 { - compatible = "nuvoton,npcx-gpio"; - reg = <0x4008b000 0x2000>; - gpio-controller; - index = <0x5>; wui-maps = <&wui_io50 &wui_io51 &wui_io52 &wui_io53 &wui_io54 &wui_io55 &wui_io56 &wui_io57>; - #gpio-cells=<2>; - label="GPIO_5"; }; gpio6: gpio@4008d000 { - compatible = "nuvoton,npcx-gpio"; - reg = <0x4008d000 0x2000>; - gpio-controller; - index = <0x6>; wui-maps = <&wui_io60 &wui_io61 &wui_io62 &wui_io63 &wui_io64 &wui_none &wui_none &wui_io67>; - #gpio-cells=<2>; - label="GPIO_6"; }; gpio7: gpio@4008f000 { - compatible = "nuvoton,npcx-gpio"; - reg = <0x4008f000 0x2000>; - gpio-controller; - index = <0x7>; wui-maps = <&wui_io70 &wui_none &wui_io72 &wui_io73 &wui_io74 &wui_io75 &wui_io76 &wui_none>; - #gpio-cells=<2>; - label="GPIO_7"; }; gpio8: gpio@40091000 { - compatible = "nuvoton,npcx-gpio"; - reg = <0x40091000 0x2000>; - gpio-controller; - index = <0x8>; wui-maps = <&wui_io80 &wui_io81 &wui_io82 &wui_io83 &wui_none &wui_none &wui_io86 &wui_io87>; - #gpio-cells=<2>; - label="GPIO_8"; }; gpio9: gpio@40093000 { - compatible = "nuvoton,npcx-gpio"; - reg = <0x40093000 0x2000>; - gpio-controller; - index = <0x9>; wui-maps = <&wui_io90 &wui_io91 &wui_io92 &wui_io93 &wui_io94 &wui_io95 &wui_io96 &wui_io97>; - #gpio-cells=<2>; - label="GPIO_9"; }; gpioa: gpio@40095000 { - compatible = "nuvoton,npcx-gpio"; - reg = <0x40095000 0x2000>; - gpio-controller; - index = <0xA>; wui-maps = <&wui_ioa0 &wui_ioa1 &wui_ioa2 &wui_ioa3 &wui_ioa4 &wui_ioa5 &wui_ioa6 &wui_ioa7>; - #gpio-cells=<2>; - label="GPIO_A"; }; gpiob: gpio@40097000 { - compatible = "nuvoton,npcx-gpio"; - reg = <0x40097000 0x2000>; - gpio-controller; - index = <0xB>; wui-maps = <&wui_iob0 &wui_iob1 &wui_iob2 &wui_iob3 &wui_iob4 &wui_iob5 &wui_none &wui_iob7>; - #gpio-cells=<2>; - label="GPIO_B"; }; gpioc: gpio@40099000 { - compatible = "nuvoton,npcx-gpio"; - reg = <0x40099000 0x2000>; - gpio-controller; - index = <0xC>; wui-maps = <&wui_ioc0 &wui_ioc1 &wui_ioc2 &wui_ioc3 &wui_ioc4 &wui_ioc5 &wui_ioc6 &wui_ioc7>; - #gpio-cells=<2>; - label="GPIO_C"; }; gpiod: gpio@4009b000 { - compatible = "nuvoton,npcx-gpio"; - reg = <0x4009b000 0x2000>; - gpio-controller; - index = <0xD>; wui-maps = <&wui_iod0 &wui_iod1 &wui_iod2 &wui_iod3 &wui_iod4 &wui_iod5 &wui_none &wui_iod7>; - #gpio-cells=<2>; - label="GPIO_D"; }; gpioe: gpio@4009d000 { - compatible = "nuvoton,npcx-gpio"; - reg = <0x4009d000 0x2000>; - gpio-controller; - index = <0xE>; wui-maps = <&wui_ioe0 &wui_ioe1 &wui_ioe2 &wui_ioe3 &wui_ioe4 &wui_ioe5 &wui_none &wui_none>; - #gpio-cells=<2>; - label="GPIO_E"; }; gpiof: gpio@4009f000 { - compatible = "nuvoton,npcx-gpio"; - reg = <0x4009f000 0x2000>; - gpio-controller; - index = <0xF>; wui-maps = <&wui_iof0 &wui_iof1 &wui_iof2 &wui_iof3 &wui_iof4 &wui_iof5 &wui_none &wui_none>; - #gpio-cells=<2>; - label="GPIO_F"; - }; - - pwm0: pwm@40080000 { - compatible = "nuvoton,npcx-pwm"; - reg = <0x40080000 0x2000>; - clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 0>; - pinctrl-0 = <&alt4_pwm0_sl>; /* PINC3 */ - #pwm-cells = <2>; - status = "disabled"; - label = "PWM_0"; - }; - - pwm1: pwm@40082000 { - compatible = "nuvoton,npcx-pwm"; - reg = <0x40082000 0x2000>; - clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 1>; - pinctrl-0 = <&alt4_pwm1_sl>; /* PINC2 */ - #pwm-cells = <2>; - status = "disabled"; - label = "PWM_1"; - }; - - pwm2: pwm@40084000 { - compatible = "nuvoton,npcx-pwm"; - reg = <0x40084000 0x2000>; - clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 2>; - pinctrl-0 = <&alt4_pwm2_sl>; /* PINC4 */ - #pwm-cells = <2>; - status = "disabled"; - label = "PWM_2"; - }; - - pwm3: pwm@40086000 { - compatible = "nuvoton,npcx-pwm"; - reg = <0x40086000 0x2000>; - clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 3>; - pinctrl-0 = <&alt4_pwm3_sl>; /* PIN80 */ - #pwm-cells = <2>; - status = "disabled"; - label = "PWM_3"; - }; - - pwm4: pwm@40088000 { - compatible = "nuvoton,npcx-pwm"; - reg = <0x40088000 0x2000>; - clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 4>; - pinctrl-0 = <&alt4_pwm4_sl>; /* PINB6 */ - #pwm-cells = <2>; - status = "disabled"; - label = "PWM_4"; - }; - - pwm5: pwm@4008a000 { - compatible = "nuvoton,npcx-pwm"; - reg = <0x4008a000 0x2000>; - clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 5>; - pinctrl-0 = <&alt4_pwm5_sl>; /* PINB7 */ - #pwm-cells = <2>; - status = "disabled"; - label = "PWM_5"; - }; - - pwm6: pwm@4008c000 { - compatible = "nuvoton,npcx-pwm"; - reg = <0x4008c000 0x2000>; - clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 6>; - pinctrl-0 = <&alt4_pwm6_sl>; /* PINC0 */ - #pwm-cells = <2>; - status = "disabled"; - label = "PWM_6"; - }; - - pwm7: pwm@4008e000 { - compatible = "nuvoton,npcx-pwm"; - reg = <0x4008e000 0x2000>; - clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 7>; - pinctrl-0 = <&alt4_pwm7_sl>; /* PIN60 */ - #pwm-cells = <2>; - status = "disabled"; - label = "PWM_7"; }; + /* Supported channels for ADC0 in npcx7 series */ adc0: adc@400d1000 { - compatible = "nuvoton,npcx-adc"; - #io-channel-cells = <1>; - reg = <0x400d1000 0x2000>; - interrupts = <10 3>; - clocks = <&pcc NPCX_CLOCK_BUS_APB1 NPCX_PWDWN_CTL4 4>; pinctrl-0 = <&alt6_adc0_sl /* ADC0 - PIN45 */ &alt6_adc1_sl /* ADC1 - PIN44 */ &alt6_adc2_sl /* ADC2 - PIN43 */ @@ -468,282 +185,6 @@ &altf_adc7_sl /* ADC7 - PINE1 */ &altf_adc8_sl /* ADC8 - PINF1 */ &altf_adc9_sl>; /* ADC9 - PINF0 */ - - status = "disabled"; - label = "ADC_0"; - }; - - twd0: watchdog@400d8000 { - compatible = "nuvoton,npcx-watchdog"; - reg = <0x400d8000 0x2000>; - t0-out = <&wui_t0out>; - label = "TWD_0"; - }; - - espi0: espi@4000a000 { - compatible = "nuvoton,npcx-espi"; - reg = <0x4000a000 0x2000>; - interrupts = <18 3>; /* Interrupt for eSPI Bus */ - - /* clocks for eSPI modules */ - clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL6 7>; - /* PIN46.47.51.52.53.54.55.57 */ - pinctrl-0 = <&alt1_no_lpc_espi>; - /* WUI maps for eSPI signals */ - espi-rst-wui = <&wui_espi_rst>; - label = "ESPI_0"; - - #address-cells = <1>; - #size-cells = <0>; - #vw-cells = <3>; - status = "disabled"; - }; - - host_sub: lpc@400c1000 { - compatible = "nuvoton,npcx-host-sub"; - /* host sub-module register address & size */ - reg = <0x400c1000 0x2000 - 0x40010000 0x2000 - 0x4000e000 0x2000 - 0x400c7000 0x2000 - 0x400c9000 0x2000 - 0x400cb000 0x2000>; - reg-names = "mswc", "shm", "c2h", "kbc", "pm_acpi", - "pm_hcmd"; - - /* host sub-module IRQ and priority */ - interrupts = <25 3>, /* KBC Input-Buf-Full (IBF) */ - <56 3>, /* KBC Output-Buf-Empty (OBE) */ - <26 3>, /* PMCH Input-Buf-Full (IBF) */ - <3 3>, /* PMCH Output-Buf-Empty (OBE) */ - <6 3>; /* Port80 FIFO Not Empty */ - interrupt-names = "kbc_ibf", "kbc_obe", "pmch_ibf", - "pmch_obe", "p80_fifo"; - - /* WUI map for accessing host sub-modules */ - host-acc-wui = <&wui_host_acc>; - - /* clocks for host sub-modules */ - clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 3>, - <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 4>, - <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 5>, - <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 6>, - <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 7>; - label = "HOST_SUBS"; - }; - - host_uart: io_host_uart { - compatible = "nuvoton,npcx-host-uart"; - /* Host serial port pinmux PIN75 86 36 33 42 C7 B3 B2 */ - pinctrl-0 = <&altb_rxd_sl &altb_txd_sl - &altb_rts_sl &altb_cts_sl - &altb_ri_sl &altb_dtr_bout_sl - &altb_dcd_sl &altb_dsr_sl>; - label = "HOST_UART_IO"; - status = "disabled"; - }; - - /* I2c Controllers - Do not use them as i2c node directly */ - i2c_ctrl0: i2c@40009000 { - compatible = "nuvoton,npcx-i2c-ctrl"; - reg = <0x40009000 0x1000>; - interrupts = <13 3>; - clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL3 0>; - label = "I2CCTRL_0"; - }; - - i2c_ctrl1: i2c@4000b000 { - compatible = "nuvoton,npcx-i2c-ctrl"; - reg = <0x4000b000 0x1000>; - interrupts = <14 3>; - clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL3 1>; - label = "I2CCTRL_1"; - }; - - i2c_ctrl2: i2c@400c0000 { - compatible = "nuvoton,npcx-i2c-ctrl"; - reg = <0x400c0000 0x1000>; - interrupts = <36 3>; - clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL3 2>; - label = "I2CCTRL_2"; - }; - - i2c_ctrl3: i2c@400c2000 { - compatible = "nuvoton,npcx-i2c-ctrl"; - reg = <0x400c2000 0x1000>; - interrupts = <37 3>; - clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL3 3>; - label = "I2CCTRL_3"; - }; - - i2c_ctrl4: i2c@40008000 { - compatible = "nuvoton,npcx-i2c-ctrl"; - reg = <0x40008000 0x1000>; - interrupts = <19 3>; - clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL3 4>; - label = "I2CCTRL_4"; - }; - - i2c_ctrl5: i2c@40017000 { - compatible = "nuvoton,npcx-i2c-ctrl"; - reg = <0x40017000 0x1000>; - interrupts = <20 3>; - clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL7 0>; - label = "I2CCTRL_5"; - }; - - i2c_ctrl6: i2c@40018000 { - compatible = "nuvoton,npcx-i2c-ctrl"; - reg = <0x40018000 0x1000>; - interrupts = <16 3>; - clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL7 1>; - label = "I2CCTRL_6"; - }; - - i2c_ctrl7: i2c@40019000 { - compatible = "nuvoton,npcx-i2c-ctrl"; - reg = <0x40019000 0x1000>; - interrupts = <8 3>; - clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL7 2>; - label = "I2CCTRL_7"; - }; - - /* I2c Ports - Please use them as i2c node */ - i2c0_0: io_i2c_ctrl0_port0 { - compatible = "nuvoton,npcx-i2c-port"; - #address-cells = <1>; - #size-cells = <0>; - port = <0x00>; - controller = <&i2c_ctrl0>; - pinctrl-0 = <&alt2_i2c0_0_sl>; /* PINB5.B4 */ - label = "I2C_0_PORT_0"; - status = "disabled"; - }; - - i2c1_0: io_i2c_ctrl1_port0 { - compatible = "nuvoton,npcx-i2c-port"; - #address-cells = <1>; - #size-cells = <0>; - port = <0x10>; - controller = <&i2c_ctrl1>; - pinctrl-0 = <&alt2_i2c1_0_sl>; /* PIN90.87 */ - label = "I2C_1_PORT_0"; - status = "disabled"; - }; - - i2c2_0: io_i2c_ctrl2_port0 { - compatible = "nuvoton,npcx-i2c-port"; - #address-cells = <1>; - #size-cells = <0>; - port = <0x20>; - controller = <&i2c_ctrl2>; - pinctrl-0 = <&alt2_i2c2_0_sl>; /* PIN92.91 */ - label = "I2C_2_PORT_0"; - status = "disabled"; - }; - - i2c3_0: io_i2c_ctrl3_port0 { - compatible = "nuvoton,npcx-i2c-port"; - #address-cells = <1>; - #size-cells = <0>; - port = <0x30>; - controller = <&i2c_ctrl3>; - pinctrl-0 = <&alt2_i2c3_0_sl>; /* PIND1.D0 */ - label = "I2C_3_PORT_0"; - status = "disabled"; - }; - - i2c4_1: io_i2c_ctrl4_port1 { - compatible = "nuvoton,npcx-i2c-port"; - #address-cells = <1>; - #size-cells = <0>; - port = <0x41>; - controller = <&i2c_ctrl4>; - pinctrl-0 = <&alt6_i2c4_1_sl>; /* PINF3.F2 */ - label = "I2C_4_PORT_1"; - status = "disabled"; - }; - - i2c5_0: io_i2c_ctrl5_port0 { - compatible = "nuvoton,npcx-i2c-port"; - #address-cells = <1>; - #size-cells = <0>; - port = <0x50>; - controller = <&i2c_ctrl5>; - pinctrl-0 = <&alt2_i2c5_0_sl>; /* PIN33.36 */ - label = "I2C_5_PORT_0"; - status = "disabled"; - }; - - i2c5_1: io_i2c_ctrl5_port1 { - compatible = "nuvoton,npcx-i2c-port"; - #address-cells = <1>; - #size-cells = <0>; - port = <0x51>; - controller = <&i2c_ctrl5>; - pinctrl-0 = <&alt6_i2c5_1_sl>; /* PINF5.F4 */ - label = "I2C_5_PORT_1"; - status = "disabled"; - }; - - i2c6_0: io_i2c_ctrl6_port0 { - compatible = "nuvoton,npcx-i2c-port"; - #address-cells = <1>; - #size-cells = <0>; - port = <0x60>; - controller = <&i2c_ctrl6>; - pinctrl-0 = <&alt2_i2c6_0_sl>; /* PINC2.C1 */ - label = "I2C_6_PORT_0"; - status = "disabled"; - }; - - i2c6_1: io_i2c_ctrl6_port1 { - compatible = "nuvoton,npcx-i2c-port"; - #address-cells = <1>; - #size-cells = <0>; - port = <0x61>; - controller = <&i2c_ctrl6>; - pinctrl-0 = <&alt6_i2c6_1_sl>; /* PINE4.E3 */ - label = "I2C_6_PORT_1"; - status = "disabled"; - }; - - i2c7_0: io_i2c_ctrl7_port0 { - compatible = "nuvoton,npcx-i2c-port"; - #address-cells = <1>; - #size-cells = <0>; - port = <0x70>; - controller = <&i2c_ctrl7>; - pinctrl-0 = <&alt2_i2c7_0_sl>; /* PINB3.B2 */ - label = "I2C_7_PORT_0"; - status = "disabled"; - }; - - tach1: tach@400e1000 { - compatible = "nuvoton,npcx-tach"; - reg = <0x400e1000 0x2000>; - clocks = <&pcc NPCX_CLOCK_BUS_LFCLK NPCX_PWDWN_CTL1 5>; - label = "TACH_1"; - status = "disabled"; - }; - - tach2: tach@400e3000 { - compatible = "nuvoton,npcx-tach"; - reg = <0x400e3000 0x2000>; - clocks = <&pcc NPCX_CLOCK_BUS_LFCLK NPCX_PWDWN_CTL1 6>; - label = "TACH_2"; - status = "disabled"; - }; - - psl_out: psl-out { - compatible = "nuvoton,npcx-psl-out"; - controller = <&gpio8>; - pin = <5>; - label = "PSL_OUT"; }; }; }; - -&nvic { - arm,num-irq-priority-bits = <3>; -};