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boards: remove pulpino board

Browse source 
This board is unmaintained and unsupported. It is not known to work and
has lots of conditional code across the tree that makes code
unmaintainable.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
Anas Nashif 2019-01-14 12:16:38 -05:00
commit a93651085e
37 changed files with 9 additions and 1603 deletions
Download patch file Download diff file Expand all files Collapse all files

2
CODEOWNERS
View file

@ -99,7 +99,6 @@ drivers/ethernet/ @jukkar @tbursztyka @pfalcon
drivers/flash/ @nashif
drivers/flash/*stm32* @superna9999
drivers/gpio/*stm32* @rsalveti @idlethread
drivers/gpio/gpio_pulpino.c @kgugala @pgielda @nategraff-sifive
drivers/i2s/i2s_ll_stm32* @avisconti
drivers/ieee802154/ @jukkar @tbursztyka
drivers/interrupt_controller/ @andrewboie
@ -117,7 +116,6 @@ drivers/net/slip.c @jukkar @tbursztyka
drivers/spi/ @tbursztyka
drivers/spi/spi_ll_stm32.* @superna9999
drivers/timer/altera_avalon_timer_hal.c @ramakrishnapallala
drivers/timer/pulpino_timer.c @nategraff-sifive @kgugala @pgielda
drivers/timer/riscv_machine_timer.c @nategraff-sifive @kgugala @pgielda
drivers/usb/ @jfischer-phytec-iot @finikorg
drivers/usb/device/usb_dc_stm32.c @ydamigos @loicpoulain

4
boards/riscv32/zedboard_pulpino/Kconfig.board
View file

@ -1,4 +0,0 @@
config BOARD_ZEDBOARD_PULPINO
bool "Zedboard pulpino target"
depends on SOC_RISCV32_PULPINO
select BUILD_OUTPUT_S19

6
boards/riscv32/zedboard_pulpino/Kconfig.defconfig
View file

@ -1,6 +0,0 @@
if BOARD_ZEDBOARD_PULPINO
config BOARD
default "zedboard_pulpino"
endif

20
boards/riscv32/zedboard_pulpino/doc/zedboard_pulpino.rst
View file

@ -1,20 +0,0 @@
.. _zedboard_pulpino:
Zedboard Pulpino
################
Overview
********
By default this board will be built without accounting for
pulpino-specific ISA. To account for them, edit
zedboard_pulpino_defconfig and set CONFIG_RISCV_GENERIC_TOOLCHAIN=n.
However, in this case, a pulpino-specific toolchain should be
use, by setting the following env variables, prior to compiling
an application.
To setup the build system with the correct toolchain use::
export RISCV32_TOOLCHAIN_PATH=~/path/to/pulpino/toolchain
export ZEPHYR_TOOLCHAIN_VARIANT=riscv32

111
boards/riscv32/zedboard_pulpino/zedboard_pulpino.dts
View file

@ -1,111 +0,0 @@
/*
* Copyright (c) 2018 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
/dts-v1/;
#include <pulpino.dtsi>
/ {
model = "zedboard_pulpino";
compatible = "pulp,zedboard-pulpino";
aliases {
uart-0 = &uart0;
gpio-0 = &gpio0;
led0 = &led0;
led1 = &led1;
led2 = &led2;
led3 = &led3;
led4 = &led4;
led5 = &led5;
led6 = &led6;
led7 = &led7;
sw0 = &btnc;
sw1 = &btnd;
sw2 = &btnl;
sw3 = &btnr;
sw4 = &btnu;
};
chosen {
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
};
leds {
compatible = "gpio-leds";
led0: led_0 {
gpios = <&gpio0 8 0>;
label = "LD0";
};
led1: led_1 {
gpios = <&gpio0 9 0>;
label = "LD1";
};
led2: led_2 {
gpios = <&gpio0 10 0>;
label = "LD2";
};
led3: led_3 {
gpios = <&gpio0 11 0>;
label = "LD3";
};
led4: led_4 {
gpios = <&gpio0 12 0>;
label = "LD4";
};
led5: led_5 {
gpios = <&gpio0 13 0>;
label = "LD5";
};
led6: led_6 {
gpios = <&gpio0 14 0>;
label = "LD6";
};
led7: led_7 {
gpios = <&gpio0 15 0>;
label = "LD7";
};
};
gpio_keys {
compatible = "gpio-keys";
/* center */
btnc: button_c {
label = "BTNC";
gpios = <&gpio0 16 (GPIO_INT_EDGE | GPIO_INT_ACTIVE_HIGH)>;
};
/* down */
btnd: button_d {
label = "BTNC";
gpios = <&gpio0 17 (GPIO_INT_EDGE | GPIO_INT_ACTIVE_HIGH)>;
};
/* left */
btnl: button_l {
label = "BTNL";
gpios = <&gpio0 18 (GPIO_INT_EDGE | GPIO_INT_ACTIVE_HIGH)>;
};
/* right */
btnr: button_r {
label = "BTNR";
gpios = <&gpio0 19 (GPIO_INT_EDGE | GPIO_INT_ACTIVE_HIGH)>;
};
/* up */
btnu: button_u {
label = "BTNU";
gpios = <&gpio0 20 (GPIO_INT_EDGE | GPIO_INT_ACTIVE_HIGH)>;
};
};
};
&uart0 {
status = "ok";
current-speed = <115200>;
};
&gpio0 {
status = "ok";
};

12
boards/riscv32/zedboard_pulpino/zedboard_pulpino.yaml
View file

@ -1,12 +0,0 @@
identifier: zedboard_pulpino
name: Zedboard Pulpino
type: mcu
arch: riscv32
toolchain:
- zephyr
ram: 32
flash: 32
testing:
ignore_tags:
- net
- bluetooth

13
boards/riscv32/zedboard_pulpino/zedboard_pulpino_defconfig
View file

@ -1,13 +0,0 @@
CONFIG_RISCV32=y
CONFIG_SOC_RISCV32_PULPINO=y
CONFIG_BOARD_ZEDBOARD_PULPINO=y
CONFIG_CONSOLE=y
CONFIG_PRINTK=y
CONFIG_SERIAL=y
CONFIG_UART_NS16550=y
CONFIG_UART_CONSOLE=y
CONFIG_UART_CONSOLE_ON_DEV_NAME="UART_0"
CONFIG_PULPINO_TIMER=y
CONFIG_GPIO=y
CONFIG_GPIO_PULPINO=y
CONFIG_BOOT_BANNER=y

1
drivers/gpio/CMakeLists.txt
View file

@ -16,7 +16,6 @@ zephyr_library_sources_ifdef(CONFIG_GPIO_MCUX_LPC gpio_mcux_lpc.c)
zephyr_library_sources_ifdef(CONFIG_GPIO_MMIO32 gpio_mmio32.c)
zephyr_library_sources_ifdef(CONFIG_GPIO_NRFX gpio_nrfx.c)
zephyr_library_sources_ifdef(CONFIG_GPIO_PCAL9535A gpio_pcal9535a.c)
zephyr_library_sources_ifdef(CONFIG_GPIO_PULPINO gpio_pulpino.c)
zephyr_library_sources_ifdef(CONFIG_GPIO_QMSI gpio_qmsi.c)
zephyr_library_sources_ifdef(CONFIG_GPIO_QMSI_SS gpio_qmsi_ss.c)
zephyr_library_sources_ifdef(CONFIG_GPIO_SCH gpio_sch.c)

2
drivers/gpio/Kconfig
View file

@ -48,8 +48,6 @@ source "drivers/gpio/Kconfig.cmsdk_ahb"
source "drivers/gpio/Kconfig.cc32xx"
source "drivers/gpio/Kconfig.pulpino"
source "drivers/gpio/Kconfig.sifive"
source "drivers/gpio/Kconfig.cc2650"

15
drivers/gpio/Kconfig.pulpino
View file

@ -1,15 +0,0 @@
# Kconfig.pulpino - pulpino GPIO configuration option
#
# Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
#
# SPDX-License-Identifier: Apache-2.0
#
menuconfig GPIO_PULPINO
bool "Pulpino GPIO controller driver"
depends on GPIO && SOC_RISCV32_PULPINO
select HAS_DTS_GPIO
help
Enable driver for the Pulpino GPIO controller.
Says n if not sure.

278
drivers/gpio/gpio_pulpino.c
View file

@ -1,278 +0,0 @@
/*
* Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file Driver for the pulpino GPIO controller.
*/
#include <errno.h>
#include <kernel.h>
#include <device.h>
#include <soc.h>
#include <gpio.h>
#include <misc/util.h>
#include "gpio_utils.h"
typedef void (*pulpino_cfg_func_t)(void);
/* pulpino GPIO register-set structure */
struct gpio_pulpino_t {
u32_t paddir;
u32_t padin;
u32_t padout;
u32_t inten;
u32_t inttype0;
u32_t inttype1;
u32_t intstatus;
};
struct gpio_pulpino_config {
u32_t gpio_base_addr;
pulpino_cfg_func_t gpio_cfg_func;
};
struct gpio_pulpino_data {
/* list of callbacks */
sys_slist_t cb;
};
/* Helper Macros for GPIO */
#define DEV_GPIO_CFG(dev) \
((const struct gpio_pulpino_config * const)(dev)->config->config_info)
#define DEV_GPIO(dev) \
((volatile struct gpio_pulpino_t *)(DEV_GPIO_CFG(dev))->gpio_base_addr)
#define DEV_GPIO_DATA(dev) \
((struct gpio_pulpino_data *)(dev)->driver_data)
static void gpio_pulpino_irq_handler(void *arg)
{
struct device *dev = (struct device *)arg;
struct gpio_pulpino_data *data = DEV_GPIO_DATA(dev);
volatile struct gpio_pulpino_t *gpio = DEV_GPIO(dev);
_gpio_fire_callbacks(&data->cb, dev, gpio->intstatus);
}
/**
* @brief Configure pin
*
* @param dev Device structure
* @param access_op Access operation
* @param pin The pin number
* @param flags Flags of pin or port
*
* @return 0 if successful, failed otherwise
*/
static int gpio_pulpino_config(struct device *dev,
int access_op,
u32_t pin,
int flags)
{
volatile struct gpio_pulpino_t *gpio = DEV_GPIO(dev);
if (access_op != GPIO_ACCESS_BY_PIN)
return -ENOTSUP;
if (pin > 31)
return -EINVAL;
/* Configure pin as gpio */
PULP_PADMUX |= (PULP_PAD_GPIO << pin);
/* Configure gpio direction */
if (flags & GPIO_DIR_OUT)
gpio->paddir |= BIT(pin);
else
gpio->paddir &= ~BIT(pin);
/*
* Configure interrupt if GPIO_INT is set.
* Here, we just configure the gpio interrupt behavior,
* we do not enable/disable interrupt for a particular
* gpio.
* Interrupt for a gpio is:
* 1) enabled only via a call to gpio_pulpino_enable_callback.
* 2) disabled only via a call to gpio_pulpino_disabled_callback.
*/
if (!(flags & GPIO_INT))
return 0;
/*
* Interrupt cannot be set for GPIO_DIR_OUT
*/
if (flags & GPIO_DIR_OUT)
return -EINVAL;
/* Double edge trigger not supported */
if (flags & GPIO_INT_DOUBLE_EDGE)
return -ENOTSUP;
/* Edge or Level triggered ? */
if (flags & GPIO_INT_EDGE)
gpio->inttype1 |= BIT(pin);
else
gpio->inttype1 &= ~BIT(pin);
/* Level High/Rising Edge ? */
if (flags & GPIO_INT_ACTIVE_HIGH)
gpio->inttype0 &= ~BIT(pin);
else
gpio->inttype0 |= BIT(pin);
return 0;
}
/**
* @brief Set the pin
*
* @param dev Device struct
* @param access_op Access operation
* @param pin The pin number
* @param value Value to set (0 or 1)
*
* @return 0 if successful, failed otherwise
*/
static int gpio_pulpino_write(struct device *dev,
int access_op,
u32_t pin,
u32_t value)
{
volatile struct gpio_pulpino_t *gpio = DEV_GPIO(dev);
if (access_op != GPIO_ACCESS_BY_PIN)
return -ENOTSUP;
if (value)
gpio->padout |= BIT(pin);
else
gpio->padout &= ~BIT(pin);
return 0;
}
/**
* @brief Read the pin
*
* @param dev Device struct
* @param access_op Access operation
* @param pin The pin number
* @param value Value of input pin(s)
*
* @return 0 if successful, failed otherwise
*/
static int gpio_pulpino_read(struct device *dev,
int access_op,
u32_t pin,
u32_t *value)
{
volatile struct gpio_pulpino_t *gpio = DEV_GPIO(dev);
if (access_op != GPIO_ACCESS_BY_PIN)
return -ENOTSUP;
/*
* If gpio is configured as output,
* read gpio value from padout register,
* otherwise read gpio value from padin register
*/
if (gpio->paddir & BIT(pin))
*value = !!(gpio->padout & BIT(pin));
else
*value = !!(gpio->padin & BIT(pin));
return 0;
}
static int gpio_pulpino_manage_callback(struct device *dev,
struct gpio_callback *callback,
bool set)
{
struct gpio_pulpino_data *data = DEV_GPIO_DATA(dev);
return _gpio_manage_callback(&data->cb, callback, set);
}
static int gpio_pulpino_enable_callback(struct device *dev,
int access_op,
u32_t pin)
{
volatile struct gpio_pulpino_t *gpio = DEV_GPIO(dev);
if (access_op != GPIO_ACCESS_BY_PIN)
return -ENOTSUP;
/* Enable interrupt for pin */
gpio->inten |= BIT(pin);
return 0;
}
static int gpio_pulpino_disable_callback(struct device *dev,
int access_op,
u32_t pin)
{
volatile struct gpio_pulpino_t *gpio = DEV_GPIO(dev);
if (access_op != GPIO_ACCESS_BY_PIN)
return -ENOTSUP;
/* Disable interrupt for pin */
gpio->inten &= ~BIT(pin);
return 0;
}
static const struct gpio_driver_api gpio_pulpino_driver = {
.config = gpio_pulpino_config,
.write = gpio_pulpino_write,
.read = gpio_pulpino_read,
.manage_callback = gpio_pulpino_manage_callback,
.enable_callback = gpio_pulpino_enable_callback,
.disable_callback = gpio_pulpino_disable_callback,
};
/**
* @brief Initialize a GPIO controller
*
* Perform basic initialization of a GPIO controller
*
* @param dev GPIO device struct
*
* @return 0
*/
static int gpio_pulpino_init(struct device *dev)
{
const struct gpio_pulpino_config *cfg = DEV_GPIO_CFG(dev);
cfg->gpio_cfg_func();
return 0;
}
static void gpio_pulpino_cfg_0(void);
static const struct gpio_pulpino_config gpio_pulpino_config0 = {
.gpio_base_addr = GPIO_0_BASE_ADDRESS,
.gpio_cfg_func = gpio_pulpino_cfg_0,
};
static struct gpio_pulpino_data gpio_pulpino_data0;
DEVICE_AND_API_INIT(gpio_pulpino_0, "gpio0", gpio_pulpino_init,
&gpio_pulpino_data0, &gpio_pulpino_config0,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&gpio_pulpino_driver);
static void gpio_pulpino_cfg_0(void)
{
IRQ_CONNECT(GPIO_0_IRQ,
0,
gpio_pulpino_irq_handler,
DEVICE_GET(gpio_pulpino_0),
0);
irq_enable(GPIO_0_IRQ);
}

1
drivers/timer/CMakeLists.txt
View file

@ -4,7 +4,6 @@ zephyr_sources_ifdef(CONFIG_ARCV2_TIMER arcv2_timer0.c)
zephyr_sources_if_kconfig( loapic_timer.c)
zephyr_sources_ifdef(CONFIG_ALTERA_AVALON_TIMER altera_avalon_timer_hal.c)
zephyr_sources_if_kconfig( nrf_rtc_timer.c)
zephyr_sources_if_kconfig( pulpino_timer.c)
zephyr_sources_if_kconfig( riscv_machine_timer.c)
zephyr_sources_if_kconfig( rv32m1_lptmr_timer.c)
zephyr_sources_if_kconfig( cortex_m_systick.c)

8
drivers/timer/Kconfig
View file

@ -118,14 +118,6 @@ config NRF_RTC_TIMER
Counter NRF_RTC1 and provides the standard "system clock driver"
interfaces.
config PULPINO_TIMER
bool "pulpino Timer"
default y
depends on SOC_RISCV32_PULPINO
help
This module implements a kernel device driver for the pulpino processor
timer driver. It provides the standard "system clock driver" interfaces.
config RISCV_MACHINE_TIMER
bool "RISCV Machine Timer"
depends on SOC_FAMILY_RISCV_PRIVILEGE

78
drivers/timer/pulpino_timer.c
View file

@ -1,78 +0,0 @@
/*
* Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <kernel.h>
#include <arch/cpu.h>
#include <device.h>
#include <system_timer.h>
/* Timer Ctrl Bitfields */
#define TIMER_CTRL_EN (1 << 0) /* Timer Enable Bit */
#define TIMER_CTRL_PRE(x) (((x) & 0x07) << 3) /* Prescaler Value */
typedef struct {
u32_t val;
u32_t ctrl;
u32_t cmp;
} pulpino_timer_t;
static volatile pulpino_timer_t *timer = (pulpino_timer_t *)PULP_TIMER_A_BASE;
static u32_t accumulated_cycle_count;
static void pulpino_timer_irq_handler(void *unused)
{
ARG_UNUSED(unused);
/* Reset counter */
timer->val = 0U;
accumulated_cycle_count += sys_clock_hw_cycles_per_tick();
z_clock_announce(1);
}
#ifdef CONFIG_TICKLESS_IDLE
#error "Tickless idle not yet implemented for pulpino timer"
#endif
int z_clock_driver_init(struct device *device)
{
ARG_UNUSED(device);
IRQ_CONNECT(PULP_TIMER_A_CMP_IRQ, 0,
pulpino_timer_irq_handler, NULL, 0);
irq_enable(PULP_TIMER_A_CMP_IRQ);
/*
* Initialize timer.
* Reset counter and set timer to generate interrupt
* every sys_clock_hw_cycles_per_tick()
*/
timer->val = 0U;
timer->cmp = sys_clock_hw_cycles_per_tick();
timer->ctrl = TIMER_CTRL_EN;
return 0;
}
/**
*
* @brief Read the platform's timer hardware
*
* This routine returns the current time in terms of timer hardware clock
* cycles.
*
* @return up counter of elapsed clock cycles
*/
u32_t _timer_cycle_get_32(void)
{
return accumulated_cycle_count + timer->val;
}
u32_t z_clock_elapsed(void)
{
return 0;
}

44
dts/bindings/gpio/pulp,pulpino-gpio.yaml
View file

@ -1,44 +0,0 @@
#
# Copyright (c) 2018, Linaro Inc.
#
# SPDX-License-Identifier: Apache-2.0
#
---
title: PULPINO GPIO Controller
version: 0.1
description: >
This is a representation of the Pulpino GPIO node
properties:
compatible:
type: string
category: required
description: compatible strings
constraint: "pulp,pulpino-gpio"
generation: define
reg:
type: int
description: mmio register space
generation: define
category: required
interrupts:
type: compound
category: required
description: required interrupts
generation: define
label:
type: string
category: required
description: Human readable string describing the device (used by Zephyr for API name)
generation: define
cell_string: GPIO
"#cells":
- pin
- flags
...

31
dts/bindings/interrupt-controller/pulpino,event-unit.yaml
View file

@ -1,31 +0,0 @@
#
# Copyright (c) 2018, Linaro Inc.
#
# SPDX-License-Identifier: Apache-2.0
#
---
title: PULPINO Event Unit
version: 0.1
description: >
This binding describes the Pulpino Event Unit
properties:
compatible:
category: required
type: string
description: compatible strings
constraint: "pulp,pulpino-event-unit"
generation: define
reg:
category: required
type: int
description: mmio register space
generation: define
base_label: PULPINO_EVENT_UNIT
"#cells":
- irq
...

67
dts/riscv32/pulpino.dtsi
View file

@ -1,67 +0,0 @@
/*
* Copyright (c) 2018 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <dt-bindings/gpio/gpio.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "pulp,ri5cy", "riscv";
reg = <0>;
};
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "pulp,pulpino-soc", "simple-bus";
ranges;
itim: itim@0 {
compatible = "pulp,pulpino0itim";
reg = <0x0 0x8000>;
};
dtim: dtim@100000 {
compatible = "pulp,pulpino-dtim";
reg = <0x100000 0x8000>;
};
uart0: uart@1a100000 {
compatible = "ns16550";
reg = <0x1a100000 0x1000>;
label = "UART_0";
clock-frequency = <2500000>;
interrupts = <24>;
interrupt-parent = <&intc>;
status = "disabled";
};
gpio0: gpio@1a101000 {
compatible = "pulp,pulpino-gpio";
gpio-controller;
reg = <0x1a101000 0x1000>;
interrupts = <25>;
interrupt-parent = <&intc>;
label = "GPIO";
status = "disabled";
#gpio-cells = <2>;
};
intc: interrupt-controller@1a104000 {
#interrupt-cells = <1>;
compatible = "pulp,pulpino-event-unit";
interrupt-controller;
reg = <0x1a104000 0x1000>;
};
};
};

4
include/arch/riscv32/arch.h
View file

@ -129,9 +129,7 @@ extern u32_t _timer_cycle_get_32(void);
#endif /*_ASMLANGUAGE */
#if defined(CONFIG_SOC_RISCV32_PULPINO)
#include <arch/riscv32/pulpino/asm_inline.h>
#elif defined(CONFIG_SOC_FAMILY_RISCV_PRIVILEGE)
#if defined(CONFIG_SOC_FAMILY_RISCV_PRIVILEGE)
#include <arch/riscv32/riscv-privilege/asm_inline.h>
#endif

21
include/arch/riscv32/pulpino/asm_inline.h
View file

@ -1,21 +0,0 @@
/*
* Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_ARCH_RISCV32_PULPINO_ASM_INLINE_H_
#define ZEPHYR_INCLUDE_ARCH_RISCV32_PULPINO_ASM_INLINE_H_
/*
* The file must not be included directly
* Include arch/cpu.h instead
*/
#if defined(__GNUC__)
#include <arch/riscv32/pulpino/asm_inline_gcc.h>
#else
#error "Supports only GNU C compiler"
#endif
#endif /* ZEPHYR_INCLUDE_ARCH_RISCV32_PULPINO_ASM_INLINE_H_ */

108
include/arch/riscv32/pulpino/asm_inline_gcc.h
View file

@ -1,108 +0,0 @@
/*
* Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_ARCH_RISCV32_PULPINO_ASM_INLINE_GCC_H_
#define ZEPHYR_INCLUDE_ARCH_RISCV32_PULPINO_ASM_INLINE_GCC_H_
#ifdef __cplusplus
extern "C" {
#endif
/*
* The file must not be included directly
* Include arch/cpu.h instead
* NOTE: only pulpino-specific NOT RISCV32
*/
#ifndef _ASMLANGUAGE
#include <toolchain.h>
/*
* Account for pulpino-specific bit manipulation opcodes only when
* CONFIG_RISCV_GENERIC_TOOLCHAIN is not set
*/
#ifndef CONFIG_RISCV_GENERIC_TOOLCHAIN
/**
*
* @brief find least significant bit set in a 32-bit word
*
* This routine finds the first bit set starting from the least significant bit
* in the argument passed in and returns the index of that bit. Bits are
* numbered starting at 1 from the least significant bit. A return value of
* zero indicates that the value passed is zero.
*
* @return least significant bit set, 0 if @a op is 0
*/
static ALWAYS_INLINE unsigned int find_lsb_set(u32_t op)
{
unsigned int ret;
if (!op)
return 0;
__asm__ volatile ("p.ff1 %[d], %[a]"
: [d] "=r" (ret)
: [a] "r" (op));
return ret + 1;
}
/**
*
* @brief find most significant bit set in a 32-bit word
*
* This routine finds the first bit set starting from the most significant bit
* in the argument passed in and returns the index of that bit. Bits are
* numbered starting at 1 from the least significant bit. A return value of
* zero indicates that the value passed is zero.
*
* @return most significant bit set, 0 if @a op is 0
*/
static ALWAYS_INLINE unsigned int find_msb_set(u32_t op)
{
unsigned int ret;
if (!op)
return 0;
__asm__ volatile ("p.fl1 %[d], %[a]"
: [d] "=r" (ret)
: [a] "r" (op));
return ret + 1;
}
#else /* CONFIG_RISCV_GENERIC_TOOLCHAIN */
/*
* When compiled with a riscv32 generic toolchain, use
* __builtin_ffs and __builtin_clz to handle respectively
* find_lsb_set and find_msb_set.
*/
static ALWAYS_INLINE unsigned int find_lsb_set(u32_t op)
{
return __builtin_ffs(op);
}
static ALWAYS_INLINE unsigned int find_msb_set(u32_t op)
{
if (!op)
return 0;
return 32 - __builtin_clz(op);
}
#endif /* CONFIG_RISCV_GENERIC_TOOLCHAIN */
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* _ASM_INLINE_GCC_PUBLIC_GCC_H */

181
include/arch/riscv32/pulpino/linker.ld
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@ -1,181 +0,0 @@
/*
* Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Linker command/script file
*
* Linker script for the pulpino platform
*/
#define _LINKER
#define _ASMLANGUAGE
#include <autoconf.h>
#include <linker/sections.h>
#include <linker/linker-defs.h>
#include <linker/linker-tool.h>
#define ROMABLE_REGION DATARAM
#define RAMABLE_REGION DATARAM
#define _VECTOR_SECTION_NAME vector
#define _EXCEPTION_SECTION_NAME exceptions
#define _RESET_SECTION_NAME reset
ENTRY(__reset)
MEMORY
{
INSTRRAM (wx) : ORIGIN = CONFIG_ITCM_BASE_ADDRESS, LENGTH = CONFIG_ITCM_SIZE
DATARAM (rw) : ORIGIN = CONFIG_DTCM_BASE_ADDRESS, LENGTH = CONFIG_DTCM_SIZE
/* Used by and documented in include/linker/intlist.ld */
IDT_LIST (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K
}
ENTRY(CONFIG_KERNEL_ENTRY)
SECTIONS
{
#include <linker/rel-sections.ld>
/*
* .plt and .iplt are here according to
* 'riscv32-zephyr-elf-ld --verbose', before text section.
*/
SECTION_PROLOGUE(.plt,,)
{
*(.plt)
}
SECTION_PROLOGUE(.iplt,,)
{
*(.iplt)
}
GROUP_START(INSTRRAM)
SECTION_PROLOGUE(_VECTOR_SECTION_NAME,,)
{
. = ALIGN(4);
KEEP(*(.vectors.*))
} GROUP_LINK_IN(INSTRRAM)
SECTION_PROLOGUE(_RESET_SECTION_NAME,,)
{
KEEP(*(.reset.*))
} GROUP_LINK_IN(INSTRRAM)
SECTION_PROLOGUE(_EXCEPTION_SECTION_NAME,,)
{
KEEP(*(".exception.entry.*"))
*(".exception.other.*")
} GROUP_LINK_IN(INSTRRAM)
SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)
{
. = ALIGN(4);
KEEP(*(.openocd_dbg))
KEEP(*(".openocd_dbg.*"))
_image_text_start = .;
*(.text)
*(".text.*")
*(.gnu.linkonce.t.*)
*(.eh_frame)
} GROUP_LINK_IN(INSTRRAM)
_image_text_end = .;
GROUP_END(INSTRRAM)
GROUP_START(RAMABLE_REGION)
#include <linker/common-rom.ld>
SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)
{
. = ALIGN(4);
*(.rodata)
*(".rodata.*")
*(.gnu.linkonce.r.*)
#ifdef CONFIG_SOC_RODATA_LD
#include <soc-rodata.ld>
#endif
} GROUP_LINK_IN(RAMABLE_REGION)
_image_ram_start = .;
#include <linker/common-ram.ld>
SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)
{
. = ALIGN(4);
*(.data)
*(".data.*")
*(.sdata .sdata.* .gnu.linkonce.s.*)
*(.sdata2 .sdata2.* .gnu.linkonce.s2.*)
#ifdef CONFIG_SOC_RWDATA_LD
#include <soc-rwdata.ld>
#endif
} GROUP_LINK_IN(RAMABLE_REGION)
SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)
{
/*
* For performance, BSS section is assumed to be 4 byte aligned and
* a multiple of 4 bytes
*/
. = ALIGN(4);
__bss_start = .;
*(.sbss)
*(".sbss.*")
*(.bss)
*(".bss.*")
COMMON_SYMBOLS
/*
* As memory is cleared in words only, it is simpler to ensure the BSS
* section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.
*/
__bss_end = ALIGN(4);
} GROUP_LINK_IN(RAMABLE_REGION)
SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)
{
/*
* This section is used for non-initialized objects that
* will not be cleared during the boot process.
*/
*(.noinit)
*(".noinit.*")
#ifdef CONFIG_SOC_NOINIT_LD
#include <soc-noinit.ld>
#endif
} GROUP_LINK_IN(RAMABLE_REGION)
_image_ram_end = .;
_end = .; /* end of image */
#ifdef CONFIG_GEN_ISR_TABLES
#include <linker/intlist.ld>
#endif
GROUP_END(RAMABLE_REGION)
#include <linker/debug-sections.ld>
}

13
soc/riscv32/pulpino/CMakeLists.txt
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@ -1,13 +0,0 @@
zephyr_include_directories(.)
zephyr_compile_options_ifndef(
CONFIG_RISCV_GENERIC_TOOLCHAIN
-march=IMXpulpv2
)
zephyr_sources(
soc_irq.S
vector.S
pulpino_irq.c
pulpino_idle.c
)

63
soc/riscv32/pulpino/Kconfig.defconfig
View file

@ -1,63 +0,0 @@
if SOC_RISCV32_PULPINO
config SOC
string
default "pulpino"
config SYS_CLOCK_HW_CYCLES_PER_SEC
int
default 5000000
config RISCV_SOC_CONTEXT_SAVE
bool
default y
config RISCV_SOC_INTERRUPT_INIT
bool
default y
config RISCV_HAS_CPU_IDLE
bool
default y
config INCLUDE_RESET_VECTOR
bool
default y
config NUM_IRQS
int
default 32
config ITCM_BASE_ADDRESS
hex
default 0x00000000
config ITCM_SIZE
hex
default 0x8000
config DTCM_BASE_ADDRESS
hex
default 0x00100000
config DTCM_SIZE
hex
default 0x8000
if UART_NS16550
config UART_NS16550_PCI
bool
default n
config UART_NS16750
bool
default y
config UART_NS16550_PORT_0
bool
default y
endif # UART_NS16550
endif # SOC_RISCV32_PULPINO

3
soc/riscv32/pulpino/Kconfig.soc
View file

@ -1,3 +0,0 @@
config SOC_RISCV32_PULPINO
bool "Pulpino SOC implementation"
select ATOMIC_OPERATIONS_C

16
soc/riscv32/pulpino/dts_fixup.h
View file

@ -1,16 +0,0 @@
/*
* Copyright (c) 2018, Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
/* SoC level DTS fixup file */
/*
* UART configuration
*/
#define DT_UART_NS16550_PORT_0_BASE_ADDR DT_NS16550_1A100000_BASE_ADDRESS
#define DT_UART_NS16550_PORT_0_IRQ DT_NS16550_1A100000_IRQ_0
#define DT_UART_NS16550_PORT_0_CLK_FREQ DT_NS16550_1A100000_CLOCK_FREQUENCY
#define CONFIG_UART_NS16550_PORT_0_BAUD_RATE DT_NS16550_1A100000_CURRENT_SPEED
#define CONFIG_UART_NS16550_PORT_0_NAME DT_NS16550_1A100000_LABEL

11
soc/riscv32/pulpino/linker.ld
View file

@ -1,11 +0,0 @@
/*
* Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @brief Linker script for pulpino
*/
#include <arch/riscv32/pulpino/linker.ld>

62
soc/riscv32/pulpino/pulpino_idle.c
View file

@ -1,62 +0,0 @@
/*
* Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <toolchain.h>
#include <irq.h>
#include <soc.h>
#include <tracing.h>
static ALWAYS_INLINE void pulpino_idle(unsigned int key)
{
z_sys_trace_idle();
/* unlock interrupts */
irq_unlock(key);
/* Put CPU core to sleep via SCR register */
PULP_SCR = 0x01;
/* Wait for interrupt */
SOC_WFI;
}
/**
*
* @brief Power save idle routine
*
* This function will be called by the kernel idle loop or possibly within
* an implementation of _sys_power_save_idle in the kernel when the
* '_sys_power_save_flag' variable is non-zero.
*
* @return N/A
*/
void k_cpu_idle(void)
{
pulpino_idle(SOC_MSTATUS_IEN);
}
/**
*
* @brief Atomically re-enable interrupts and enter low power mode
*
* INTERNAL
* The requirements for k_cpu_atomic_idle() are as follows:
* 1) The enablement of interrupts and entering a low-power mode needs to be
* atomic, i.e. there should be no period of time where interrupts are
* enabled before the processor enters a low-power mode. See the comments
* in k_lifo_get(), for example, of the race condition that
* occurs if this requirement is not met.
*
* 2) After waking up from the low-power mode, the interrupt lockout state
* must be restored as indicated in the 'imask' input parameter.
*
* @return N/A
*/
void k_cpu_atomic_idle(unsigned int key)
{
pulpino_idle(key);
}

52
soc/riscv32/pulpino/pulpino_irq.c
View file

@ -1,52 +0,0 @@
/*
* Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief pulpino interrupt management code
*/
#include <irq.h>
#include <soc.h>
void _arch_irq_enable(unsigned int irq)
{
unsigned int key;
key = irq_lock();
/*
* enable both IRQ and Event
* Event will allow system to wakeup upon an interrupt,
* if CPU was set to sleep
*/
PULP_IER |= (1 << irq);
PULP_EER |= (1 << irq);
irq_unlock(key);
};
void _arch_irq_disable(unsigned int irq)
{
unsigned int key;
key = irq_lock();
PULP_IER &= ~(1 << irq);
PULP_EER &= ~(1 << irq);
irq_unlock(key);
};
int _arch_irq_is_enabled(unsigned int irq)
{
return !!(PULP_IER & (1 << irq));
}
#if defined(CONFIG_RISCV_SOC_INTERRUPT_INIT)
void soc_interrupt_init(void)
{
/* ensure that all interrupts are disabled */
(void)irq_lock();
PULP_IER = 0;
PULP_EER = 0;
}
#endif

141
soc/riscv32/pulpino/soc.h
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@ -1,141 +0,0 @@
/*
* Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file SoC configuration macros for the pulpino core
*/
#ifndef __PULPINO_SOC_H_
#define __PULPINO_SOC_H_
/* CSR Registers */
#define PULP_MESTATUS 0x7C0 /* Machine Exception Status Register */
#define PULP_LPSTART0 0x7B0 /* Hardware Loop 0 Start Register */
#define PULP_LPEND0 0x7B1 /* Hardware Loop 0 End Register */
#define PULP_LPCOUNT0 0x7B2 /* Hardware Loop 0 Count Register */
#define PULP_LPSTART1 0x7B4 /* Hardware Loop 1 Start Register */
#define PULP_LPEND1 0x7B5 /* Hardware Loop 1 End Register */
#define PULP_LPCOUNT1 0x7B6 /* Hardware Loop 1 Count Register */
/* IRQ numbers */
#define PULP_I2C_0_IRQ 23 /* I2C Controller */
#define PULP_SPI_0_IRQ 26 /* SPI Controller #0 */
#define PULP_SPI_1_IRQ 27 /* SPI Controller #1 */
#define PULP_TIMER_A_OVERFLOW_IRQ 28 /* Timer Overflow A */
#define PULP_TIMER_A_CMP_IRQ 29 /* Timer Output Cmp A */
#define PULP_TIMER_B_OVERFLOW_IRQ 30 /* Timer Overflow B */
#define PULP_TIMER_B_CMP_IRQ 31 /* Timer Output Cmp B */
/* min value to consider as IRQ in MCAUSE register */
#define PULP_MIN_IRQ PULP_I2C_0_IRQ
/* Exception numbers */
#define PULP_ECALL_EXP 11 /* ECALL Instruction */
/*
* SOC-specific MSTATUS related info
*/
/* MSTATUS register to save/restore upon interrupt/exception/context switch */
#define SOC_MSTATUS_REG PULP_MESTATUS
#define SOC_MSTATUS_IEN (1 << 0) /* Machine Interrupt Enable bit */
/*
* Default MSTATUS register value to restore from stack
* upon scheduling a thread for the first time
*/
#define SOC_MSTATUS_DEF_RESTORE SOC_MSTATUS_IEN
/* SOC-specific MCAUSE bitfields */
#define SOC_MCAUSE_EXP_MASK 0x1F /* Exception code Mask */
#define SOC_MCAUSE_ECALL_EXP PULP_ECALL_EXP /* ECALL exception number */
/* SOC-Specific EXIT ISR command */
#define SOC_ERET eret
/* UART configuration */
#define CONFIG_UART_NS16550_PORT_0_IRQ_PRI 0
#define DT_UART_NS16550_PORT_0_IRQ_FLAGS 0
/* PAD configuration */
#define PULP_PAD_BASE 0x1A107000
/* IRQ configuration */
#define PULP_IRQ_BASE PULPINO_EVENT_UNIT_BASE_ADDRESS
#define PULP_IER_ADDR (PULP_IRQ_BASE + 0x00) /* IRQ Enable Register */
#define PULP_IPR_ADDR (PULP_IRQ_BASE + 0x04) /* IRQ Pending Register */
#define PULP_ISP_ADDR (PULP_IRQ_BASE + 0x08) /* IRQ Set Pending Register */
#define PULP_ICP_ADDR (PULP_IRQ_BASE + 0x0C) /* IRQ Clear Pending Register */
#define PULP_EER_ADDR (PULP_IRQ_BASE + 0x10) /* Event Enable Register */
#define PULP_EPR_ADDR (PULP_IRQ_BASE + 0x14) /* Event Pending Register */
#define PULP_ESP_ADDR (PULP_IRQ_BASE + 0x18) /* Event Set Pending Register */
#define PULP_ECP_ADDR (PULP_IRQ_BASE + 0x1C) /* Event Clear Pending Register */
#define PULP_SCR_ADDR (PULP_IRQ_BASE + 0x20) /* Sleep Control Register */
/* Timer configuration */
#define PULP_TIMER_A_BASE 0x1A103000
#define PULP_TIMER_B_BASE 0x1A103010
/*
* Zephyr-SDK makes use a the latest generic riscv32 toolchain, which
* encodes the wfi opcode as 0x10500073. Pulpino does not understand
* this opcode and will generate a fault upon execution. Pulpino core
* implementation is based on a previous RISC-V ISA specification and
* expects the wfi opcode to be encoded as 0x10200073. In new toolchain,
* 0x10200073 opcode is used to represent the sret opcode. Hence,
* when compiled with a generic riscv32 toolchain, define wfi by sret
* in assembly code.
*/
#if defined(CONFIG_RISCV_GENERIC_TOOLCHAIN)
#define wfi sret
#endif
#ifndef _ASMLANGUAGE
#include <irq.h>
/* Register Access MACRO */
#define PULP_REG(x) (*((volatile unsigned int *)(x)))
/* Interrupt Registers */
#define PULP_IER PULP_REG(PULP_IER_ADDR)
#define PULP_IPR PULP_REG(PULP_IPR_ADDR)
#define PULP_ISP PULP_REG(PULP_ISP_ADDR)
#define PULP_ICP PULP_REG(PULP_ICP_ADDR)
#define PULP_EER PULP_REG(PULP_EER_ADDR)
#define PULP_EPR PULP_REG(PULP_EPR_ADDR)
#define PULP_ESP PULP_REG(PULP_ESP_ADDR)
#define PULP_ECP PULP_REG(PULP_ECP_ADDR)
#define PULP_SCR PULP_REG(PULP_SCR_ADDR)
/* PAD MUX register */
#define PULP_PADMUX PULP_REG(PULP_PAD_BASE)
#define PULP_PAD_SPI 0
#define PULP_PAD_GPIO 1
#define PULP_PAD_MASK 1
#if defined(CONFIG_RISCV_SOC_INTERRUPT_INIT)
void soc_interrupt_init(void);
#endif
/*
* when a generic riscv32 toolchain is used replaced wfi by sret
* in inline assembly. Explanation given above.
*/
#if defined(CONFIG_RISCV_GENERIC_TOOLCHAIN)
#define SOC_WFI __asm__ volatile("sret")
#else
#define SOC_WFI __asm__ volatile("wfi")
#endif
/* lib-c hooks required RAM defined variables */
#define RISCV_RAM_BASE CONFIG_DTCM_BASE_ADDRESS
#define RISCV_RAM_SIZE CONFIG_DTCM_SIZE
#endif /* !_ASMLANGUAGE */
#endif /* __PULPINO_SOC_H_ */

41
soc/riscv32/pulpino/soc_context.h
View file

@ -1,41 +0,0 @@
/*
* Copyright (c) 2018 Foundries.io Ltd
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Extra definitions required for CONFIG_RISCV_SOC_CONTEXT_SAVE.
*/
#ifndef PULPINO_SOC_CONTEXT_H_
#define PULPINO_SOC_CONTEXT_H_
/* Extra state for pulpino hardware loop registers. */
#define SOC_ESF_MEMBERS \
u32_t lpstart0; \
u32_t lpend0; \
u32_t lpcount0; \
u32_t lpstart1; \
u32_t lpend1; \
u32_t lpcount1
/* Initial saved state. */
#define SOC_ESF_INIT \
0xdeadbaad, \
0xdeadbaad, \
0xdeadbaad, \
0xdeadbaad, \
0xdeadbaad, \
0xdeadbaad
/* Ensure offset macros are available in <offsets.h> for the above. */
#define GEN_SOC_OFFSET_SYMS() \
GEN_OFFSET_SYM(soc_esf_t, lpstart0); \
GEN_OFFSET_SYM(soc_esf_t, lpend0); \
GEN_OFFSET_SYM(soc_esf_t, lpcount0); \
GEN_OFFSET_SYM(soc_esf_t, lpstart1); \
GEN_OFFSET_SYM(soc_esf_t, lpend1); \
GEN_OFFSET_SYM(soc_esf_t, lpcount1)
#endif

116
soc/riscv32/pulpino/soc_irq.S
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@ -1,116 +0,0 @@
/*
* Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
* Copyright (c) 2018 Foundries.io Ltd
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <kernel_structs.h>
#include <offsets.h>
#include <toolchain.h>
#include <linker/sections.h>
#include <soc.h>
/* exports */
GTEXT(__soc_save_context)
GTEXT(__soc_restore_context)
GTEXT(__soc_is_irq)
GTEXT(__soc_handle_irq)
GTEXT(__soc_irq_unlock)
/* Use ABI name of registers for the sake of simplicity */
#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
/*
* The Pulpino core has ISA extensions for faster loop performance
* that use extra registers.
*
* If the toolchain generates instructions that use them, they must be saved
* prior to handling an interrupt/exception. This case is handled using
* Zephyr's generic RISC-V mechanism for soc-specific context.
*
* For details, see the Kconfig help for CONFIG_RISCV_SOC_CONTEXT_SAVE.
*/
SECTION_FUNC(exception.other, __soc_save_context)
/* Save hardware loop registers to the soc_esf_t passed in a0. */
csrr t0, PULP_LPSTART0
csrr t1, PULP_LPEND0
csrr t2, PULP_LPCOUNT0
sw t0, __soc_esf_t_lpstart0_OFFSET(a0)
sw t1, __soc_esf_t_lpend0_OFFSET(a0)
sw t2, __soc_esf_t_lpcount0_OFFSET(a0)
csrr t0, PULP_LPSTART1
csrr t1, PULP_LPEND1
csrr t2, PULP_LPCOUNT1
sw t0, __soc_esf_t_lpstart1_OFFSET(a0)
sw t1, __soc_esf_t_lpend1_OFFSET(a0)
sw t2, __soc_esf_t_lpcount1_OFFSET(a0)
/* Return */
jalr x0, ra
SECTION_FUNC(exception.other, __soc_restore_context)
/* Restore hardware loop registers from soc_esf_t in a0. */
lw t0, __soc_esf_t_lpstart0_OFFSET(a0)
lw t1, __soc_esf_t_lpend0_OFFSET(a0)
lw t2, __soc_esf_t_lpcount0_OFFSET(a0)
csrw PULP_LPSTART0, t0
csrw PULP_LPEND0, t1
csrw PULP_LPCOUNT0, t2
lw t0, __soc_esf_t_lpstart1_OFFSET(a0)
lw t1, __soc_esf_t_lpend1_OFFSET(a0)
lw t2, __soc_esf_t_lpcount1_OFFSET(a0)
csrw PULP_LPSTART1, t0
csrw PULP_LPEND1, t1
csrw PULP_LPCOUNT1, t2
/* Return */
jalr x0, ra
#endif /* CONFIG_RISCV_SOC_CONTEXT_SAVE */
/*
* SOC-specific function to handle pending IRQ number generating the interrupt.
*
* The pulpino core has:
* 1) an ICP register, which is used to clear the pending
* IRQ number upon an interrupt.
* 2) an ECP register, which is used to clear the pending IRQ number
* that has woken up the CPU from sleep state.
*
* Exception number is given as parameter via register a0.
*/
SECTION_FUNC(exception.other, __soc_handle_irq)
/* Clear exception number from the Interrupt pending register */
li t1, PULP_ICP_ADDR
li t2, 1
sll t3, t2, a0
sw t3, 0x00(t1)
/* Clear exception number from the Event pending register */
li t1, PULP_ECP_ADDR
sw t3, 0x00(t1)
/* Return */
jalr x0, ra
/*
* SOC-specific function to determine if the exception is the result of a
* an interrupt or an exception
* return 1 (interrupt) or 0 (exception)
*/
SECTION_FUNC(exception.other, __soc_is_irq)
/* Get exception number from the mcause CSR register. */
csrr t0, mcause
andi t0, t0, SOC_MCAUSE_EXP_MASK
/* if IRQ number < PULP_MIN_IRQ, not interrupt */
li t1, PULP_MIN_IRQ
addi a0, x0, 0
blt t0, t1, not_interrupt
addi a0, a0, 1
not_interrupt:
/* return */
jalr x0, ra

68
soc/riscv32/pulpino/vector.S
View file

@ -1,68 +0,0 @@
/*
* Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
* Contributors: 2018 Antmicro <www.antmicro.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <toolchain.h>
/* exports */
GTEXT(__start)
/* imports */
GTEXT(__reset)
GTEXT(__irq_wrapper)
/*
* following pulpino datasheet, addr 0x00000000 - 0x00000058 are not used
* in IVT. Hence, set them to nop.
*
* Call __irq_wrapper to handle all interrupts/exceptions/faults/ECALL
*
* ECALL is used to handle context switching of threads, as well as
* IRQ offloading (when enabled).
*
* Interrupt Line 23: I2C IRQ 0x0000005C
* Interrupt Line 24: UART IRQ 0x00000060
* Interrupt Line 25: GPIO IRQ 0x00000064
* Interrupt Line 26: SPI Master 0 0x00000068
* Interrupt Line 27: SPI Master 1 0x0000006C
* Interrupt Line 28: Timer A Overflow 0x00000070
* Interrupt Line 29: Timer A Output Cmp 0x00000074
* Interrupt Line 30: Timer B Overflow 0x00000078
* Interrupt Line 31: Timer B Output Cmp 0x0000007C
*
* RESET 0x00000080 - call __reset
* Illegal Instruction Exception 0x00000084
* ECALL Instruction 0x00000088
* Invalid Memory Access 0x0000008C
*/
SECTION_FUNC(vectors, __start)
.option norvc;
/* nop addr 0x00000000 - 0x00000058 */
.org 0x00
.rept 23
nop
.endr
/* Call __irq_wrapper for all interrupts */
.org 0x5C
.rept 9
jal x0, __irq_wrapper
.endr
/* Call __reset for reset vector */
.org 0x80
jal x0, __reset
/* Illegal instruction */
jal x0, __irq_wrapper
/* ECALL (system call) */
jal x0, __irq_wrapper
/* Invalid memory access */
jal x0, __irq_wrapper

10
tests/drivers/build_all/testcase.yaml
View file

@ -11,21 +11,21 @@ tests:
extra_args: CONF_FILE=ethernet.conf
min_flash: 42
min_ram: 32
platform_exclude: zedboard_pulpino frdm_kw41z
platform_exclude: frdm_kw41z
tags: drivers footprint
depends_on: spi netif
test_build_sensors_trigger_a_h:
build_only: true
extra_args: CONF_FILE=sensors_trigger_a_h.conf
min_ram: 32
platform_exclude: zedboard_pulpino frdm_kw41z
platform_exclude: frdm_kw41z
tags: drivers footprint
depends_on: adc spi
test_build_sensors_trigger_i_z:
build_only: true
extra_args: CONF_FILE=sensors_trigger_i_z.conf
min_ram: 32
platform_exclude: zedboard_pulpino frdm_kw41z
platform_exclude: frdm_kw41z
tags: drivers footprint
depends_on: adc spi
test_build_sensors_a_h:
@ -33,7 +33,7 @@ tests:
extra_args: CONF_FILE=sensors_a_h.conf
min_flash: 44
min_ram: 32
platform_exclude: zedboard_pulpino frdm_kw41z
platform_exclude: frdm_kw41z
tags: drivers footprint
depends_on: adc spi
# FIXME see #7703
@ -43,7 +43,7 @@ tests:
build_only: true
extra_args: CONF_FILE=sensors_i_z.conf
min_ram: 32
platform_exclude: zedboard_pulpino frdm_kw41z
platform_exclude: frdm_kw41z
tags: drivers footprint
depends_on: adc spi
test_clock:

2
tests/kernel/context/src/main.c
View file

@ -64,8 +64,6 @@
#define TICK_IRQ TIMER_0_IRQ
#elif defined(CONFIG_ARCV2_TIMER)
#define TICK_IRQ IRQ_TIMER0
#elif defined(CONFIG_PULPINO_TIMER)
#define TICK_IRQ PULP_TIMER_A_CMP_IRQ
#elif defined(CONFIG_RISCV_MACHINE_TIMER)
#define TICK_IRQ RISCV_MACHINE_TIMER_IRQ
#elif defined(CONFIG_CPU_CORTEX_M)

4
tests/kernel/gen_isr_table/src/main.c
View file

@ -18,7 +18,7 @@ extern u32_t _irq_vector_table[];
#define ISR1_OFFSET 0
#define ISR2_OFFSET 1
#if defined(CONFIG_RISCV32) && !defined(CONFIG_SOC_RISCV32_PULPINO)
#if defined(CONFIG_RISCV32)
/* RISC-V has very few IRQ lines which can be triggered from software */
#define ISR3_OFFSET 1
#define ISR5_OFFSET 5
@ -56,7 +56,7 @@ void trigger_irq(int irq)
NVIC->STIR = irq;
#endif
}
#elif defined(CONFIG_RISCV32) && !defined(CONFIG_SOC_RISCV32_PULPINO)
#elif defined(CONFIG_RISCV32)
void trigger_irq(int irq)
{
u32_t mip;

2
tests/kernel/interrupt/src/interrupt.h
View file

@ -24,7 +24,7 @@ static void trigger_irq(int irq)
#endif
}
#elif defined(CONFIG_RISCV32) && !defined(CONFIG_SOC_RISCV32_PULPINO)
#elif defined(CONFIG_RISCV32)
static void trigger_irq(int irq)
{
u32_t mip;

1
tests/kernel/xip/testcase.yaml
View file

@ -1,6 +1,5 @@
tests:
arch.common.xip:
arch_exclude: xtensa
filter: not CONFIG_SOC_RISCV32_PULPINO
platform_exclude: cc3220sf_launchxl
tags: xip