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soc: riscv: sifive-freedom: fe310: Support custom coreclk rate in DTS.

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Allow coreclk to be configured up to 320 MHz from DTS.

Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com>
This commit is contained in:
Shawn Nematbakhsh 2022-03-28 15:55:50 -07:00 • committed by Carles Cufí
commit a8ffd19281
2 changed files with 42 additions and 6 deletions
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5
boards/riscv/hifive1_revb/hifive1_revb.dts
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@ -71,6 +71,11 @@
};
};
&coreclk {
clock-frequency = <DT_FREQ_M(16)>;
status = "okay";
};
&gpio0 {
status = "okay";
};