arm: cortex-m: clean up some more hard-coded constants in swap_helper
Clean up a few more hard-coded constants in swap_helper.S and replace them with CMSIS-like defines in cpu.h. No behavioral changes in this commit. Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
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03c4bcd920
commit
a8d6c14d30
2 changed files with 17 additions and 6 deletions
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@ -20,13 +20,15 @@
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#include <arch/cpu.h>
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#include <syscall.h>
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#if defined(CONFIG_CPU_CORTEX_M)
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#include <arch/arm/aarch32/cortex_m/cpu.h>
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#endif
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_ASM_FILE_PROLOGUE
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GTEXT(z_arm_svc)
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GTEXT(z_arm_pendsv)
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GTEXT(z_do_kernel_oops)
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GTEXT(z_arm_do_syscall)
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GDATA(_k_neg_eagain)
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GDATA(_kernel)
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@ -100,7 +102,7 @@ SECTION_FUNC(TEXT, z_arm_pendsv)
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stmia r0, {v1-v8, ip}
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#ifdef CONFIG_FPU_SHARING
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/* Assess whether switched-out thread had been using the FP registers. */
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tst lr, #0x10 /* EXC_RETURN & EXC_RETURN.F_Type_Msk */
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tst lr, #_EXC_RETURN_FTYPE_Msk
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bne out_fp_endif
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/* FP context active: set FP state and store callee-saved registers.
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@ -287,7 +289,7 @@ _thread_irq_disabled:
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#ifdef CONFIG_FPU_SHARING
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/* Assess whether switched-in thread had been using the FP registers. */
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tst lr, #0x10 /* EXC_RETURN & EXC_RETURN.F_Type_Msk */
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tst lr, #_EXC_RETURN_FTYPE_Msk
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beq in_fp_active
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/* FP context inactive for swapped-in thread:
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* - reset FPSCR to 0
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@ -309,7 +311,7 @@ in_fp_active:
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in_fp_endif:
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/* Clear CONTROL.FPCA that may have been set by FP instructions */
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mrs r3, CONTROL
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bic r3, #0x4 /* CONTROL.FPCA Msk */
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bic r3, #_CONTROL_FPCA_Msk
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msr CONTROL, r3
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isb
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#endif
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@ -408,7 +410,7 @@ SECTION_FUNC(TEXT, z_arm_svc)
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* MSP or PSP
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*/
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#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
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movs r0, #0x4
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movs r0, #_EXC_RETURN_SPSEL_Msk
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mov r1, lr
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tst r1, r0
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beq _stack_frame_msp
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@ -418,7 +420,7 @@ _stack_frame_msp:
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mrs r0, MSP
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_stack_frame_endif:
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#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
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tst lr, #0x4 /* did we come from thread mode ? */
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tst lr, #_EXC_RETURN_SPSEL_Msk /* did we come from thread mode ? */
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ite eq /* if zero (equal), came from handler mode */
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mrseq r0, MSP /* handler mode, stack frame is on MSP */
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mrsne r0, PSP /* thread mode, stack frame is on PSP */
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@ -10,12 +10,21 @@
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#ifdef _ASMLANGUAGE
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#define _SCS_BASE_ADDR _PPB_INT_SCS
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/* ICSR defines */
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#define _SCS_ICSR (_SCS_BASE_ADDR + 0xd04)
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#define _SCS_ICSR_PENDSV (1 << 28)
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#define _SCS_ICSR_UNPENDSV (1 << 27)
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#define _SCS_ICSR_RETTOBASE (1 << 11)
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#define _SCS_MPU_CTRL (_SCS_BASE_ADDR + 0xd94)
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/* CONTROL defines */
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#define _CONTROL_FPCA_Msk (1 << 2)
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/* EXC_RETURN defines */
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#define _EXC_RETURN_SPSEL_Msk (1 << 2)
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#define _EXC_RETURN_FTYPE_Msk (1 << 4)
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#endif
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#endif
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