drivers/spi: Enable port 3 and 4 on DW driver
This will be useful on Quark_SE ARC core which can access x86 core SPI controller. Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This commit is contained in:
Tomasz Bursztyka
Carles Cufí
parent
29f8b23bfd
commit
a863494463
4 changed files with 162 additions and 4 deletions
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@ -80,4 +80,59 @@ config SPI_DW_PORT_1_CLOCK_GATE_SUBSYS
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endif # SPI_DW_PORT_1_CLOCK_GATE
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endif # SPI_1
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if SPI_2
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config SPI_DW_PORT_2_INTERRUPT_SINGLE_LINE
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bool "Single interrupt line for all interrupts"
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default y
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help
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Only one line is used to trigger interrupts: RX, TX and ERROR
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interrupt go all through that line, undifferentiated.
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config SPI_DW_PORT_2_CLOCK_GATE
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bool "Enable clock gating"
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depends on CLOCK_CONTROL
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default n
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if SPI_DW_PORT_2_CLOCK_GATE
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config SPI_DW_PORT_2_CLOCK_GATE_DRV_NAME
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string
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default ""
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config SPI_DW_PORT_2_CLOCK_GATE_SUBSYS
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int "Clock controller's subsystem"
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endif # SPI_DW_PORT_2_CLOCK_GATE
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endif # SPI_2
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if SPI_3
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config SPI_DW_PORT_3_INTERRUPT_SINGLE_LINE
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bool "Single interrupt line for all interrupts"
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default y
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help
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Only one line is used to trigger interrupts: RX, TX and ERROR
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interrupt go all through that line, undifferentiated.
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config SPI_DW_PORT_3_CLOCK_GATE
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bool "Enable clock gating"
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depends on CLOCK_CONTROL
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default n
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if SPI_DW_PORT_3_CLOCK_GATE
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config SPI_DW_PORT_3_CLOCK_GATE_DRV_NAME
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string
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default ""
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config SPI_DW_PORT_3_CLOCK_GATE_SUBSYS
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int "Clock controller's subsystem"
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endif # SPI_DW_PORT_3_CLOCK_GATE
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endif # SPI_3
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endif # SPI_DW
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@ -546,3 +546,97 @@ void spi_config_1_irq(void)
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#endif
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}
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#endif /* CONFIG_SPI_1 */
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#ifdef CONFIG_SPI_2
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void spi_config_2_irq(void);
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struct spi_dw_data spi_dw_data_port_2 = {
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SPI_CONTEXT_INIT_LOCK(spi_dw_data_port_2, ctx),
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SPI_CONTEXT_INIT_SYNC(spi_dw_data_port_2, ctx),
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};
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static const struct spi_dw_config spi_dw_config_2 = {
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.regs = SPI_DW_PORT_2_REGS,
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#ifdef CONFIG_SPI_DW_PORT_2_CLOCK_GATE
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.clock_name = CONFIG_SPI_DW_PORT_2_CLOCK_GATE_DRV_NAME,
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.clock_data = UINT_TO_POINTER(CONFIG_SPI_DW_PORT_2_CLOCK_GATE_SUBSYS),
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#endif /* CONFIG_SPI_DW_PORT_2_CLOCK_GATE */
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.config_func = spi_config_2_irq
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};
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DEVICE_AND_API_INIT(spi_dw_port_2, CONFIG_SPI_2_NAME, spi_dw_init,
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&spi_dw_data_port_2, &spi_dw_config_2,
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POST_KERNEL, CONFIG_SPI_INIT_PRIORITY,
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&dw_spi_api);
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void spi_config_2_irq(void)
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{
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#ifdef CONFIG_SPI_DW_PORT_2_INTERRUPT_SINGLE_LINE
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IRQ_CONNECT(SPI_DW_PORT_2_IRQ, CONFIG_SPI_2_IRQ_PRI,
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spi_dw_isr, DEVICE_GET(spi_dw_port_2), SPI_DW_IRQ_FLAGS);
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irq_enable(SPI_DW_PORT_2_IRQ);
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_spi_int_unmask(SPI_DW_PORT_2_INT_MASK);
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#else
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IRQ_CONNECT(IRQ_SPI2_RX_AVAIL, CONFIG_SPI_2_IRQ_PRI,
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spi_dw_isr, DEVICE_GET(spi_dw_port_2), SPI_DW_IRQ_FLAGS);
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IRQ_CONNECT(IRQ_SPI2_TX_REQ, CONFIG_SPI_2_IRQ_PRI,
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spi_dw_isr, DEVICE_GET(spi_dw_port_2), SPI_DW_IRQ_FLAGS);
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IRQ_CONNECT(IRQ_SPI2_ERR_INT, CONFIG_SPI_2_IRQ_PRI,
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spi_dw_isr, DEVICE_GET(spi_dw_port_2), SPI_DW_IRQ_FLAGS);
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irq_enable(IRQ_SPI2_RX_AVAIL);
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irq_enable(IRQ_SPI2_TX_REQ);
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irq_enable(IRQ_SPI2_ERR_INT);
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_spi_int_unmask(SPI_DW_PORT_2_RX_INT_MASK);
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_spi_int_unmask(SPI_DW_PORT_2_TX_INT_MASK);
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_spi_int_unmask(SPI_DW_PORT_2_ERROR_INT_MASK);
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#endif
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}
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#endif /* CONFIG_SPI_2 */
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#ifdef CONFIG_SPI_3
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void spi_config_3_irq(void);
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struct spi_dw_data spi_dw_data_port_3 = {
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SPI_CONTEXT_INIT_LOCK(spi_dw_data_port_3, ctx),
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SPI_CONTEXT_INIT_SYNC(spi_dw_data_port_3, ctx),
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};
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static const struct spi_dw_config spi_dw_config_3 = {
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.regs = SPI_DW_PORT_3_REGS,
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#ifdef CONFIG_SPI_DW_PORT_3_CLOCK_GATE
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.clock_name = CONFIG_SPI_DW_PORT_3_CLOCK_GATE_DRV_NAME,
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.clock_data = UINT_TO_POINTER(CONFIG_SPI_DW_PORT_3_CLOCK_GATE_SUBSYS),
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#endif /* CONFIG_SPI_DW_PORT_3_CLOCK_GATE */
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.config_func = spi_config_3_irq
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};
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DEVICE_AND_API_INIT(spi_dw_port_3, CONFIG_SPI_3_NAME, spi_dw_init,
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&spi_dw_data_port_3, &spi_dw_config_3,
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POST_KERNEL, CONFIG_SPI_INIT_PRIORITY,
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&dw_spi_api);
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void spi_config_3_irq(void)
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{
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#ifdef CONFIG_SPI_DW_PORT_3_INTERRUPT_SINGLE_LINE
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IRQ_CONNECT(SPI_DW_PORT_3_IRQ, CONFIG_SPI_3_IRQ_PRI,
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spi_dw_isr, DEVICE_GET(spi_dw_port_3), SPI_DW_IRQ_FLAGS);
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irq_enable(SPI_DW_PORT_3_IRQ);
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_spi_int_unmask(SPI_DW_PORT_3_INT_MASK);
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#else
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IRQ_CONNECT(IRQ_SPI3_RX_AVAIL, CONFIG_SPI_3_IRQ_PRI,
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spi_dw_isr, DEVICE_GET(spi_dw_port_3), SPI_DW_IRQ_FLAGS);
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IRQ_CONNECT(IRQ_SPI3_TX_REQ, CONFIG_SPI_3_IRQ_PRI,
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spi_dw_isr, DEVICE_GET(spi_dw_port_3), SPI_DW_IRQ_FLAGS);
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IRQ_CONNECT(IRQ_SPI3_ERR_INT, CONFIG_SPI_3_IRQ_PRI,
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spi_dw_isr, DEVICE_GET(spi_dw_port_3), SPI_DW_IRQ_FLAGS);
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irq_enable(IRQ_SPI3_RX_AVAIL);
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irq_enable(IRQ_SPI3_TX_REQ);
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irq_enable(IRQ_SPI3_ERR_INT);
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_spi_int_unmask(SPI_DW_PORT_3_RX_INT_MASK);
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_spi_int_unmask(SPI_DW_PORT_3_TX_INT_MASK);
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_spi_int_unmask(SPI_DW_PORT_3_ERROR_INT_MASK);
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#endif
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}
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#endif /* CONFIG_SPI_3 */
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@ -195,6 +195,10 @@ struct spi_dw_data {
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#include "spi_dw_quark_se_ss_regs.h"
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#else
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#include "spi_dw_regs.h"
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#define _extra_clock_on(...)
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#define _extra_clock_off(...)
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#endif
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/* Interrupt mask
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@ -226,6 +230,9 @@ DEFINE_TEST_BIT_OP(ssienr, DW_SPI_REG_SSIENR, DW_SPI_SSIENR_SSIEN_BIT)
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DEFINE_TEST_BIT_OP(sr_busy, DW_SPI_REG_SR, DW_SPI_SR_BUSY_BIT)
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#ifdef CONFIG_CLOCK_CONTROL
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#include <string.h>
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static inline int _clock_config(struct device *dev)
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{
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const struct spi_dw_config *info = dev->config->config_info;
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@ -253,6 +260,8 @@ static inline void _clock_on(struct device *dev)
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clock_control_on(spi->clock, info->clock_data);
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}
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_extra_clock_on(dev);
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}
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static inline void _clock_off(struct device *dev)
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@ -264,6 +273,8 @@ static inline void _clock_off(struct device *dev)
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clock_control_off(spi->clock, info->clock_data);
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}
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_extra_clock_off(dev);
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}
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#else
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#define _clock_config(...)
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@ -132,16 +132,14 @@ static inline u32_t read_dr(u32_t addr)
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DEFINE_SET_BIT_OP(clk_ena, DW_SPI_REG_CTRLR0, DW_SPI_CTRLR0_CLK_ENA_BIT)
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DEFINE_CLEAR_BIT_OP(clk_ena, DW_SPI_REG_CTRLR0, DW_SPI_CTRLR0_CLK_ENA_BIT)
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#define _clock_config(...)
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static inline void _clock_on(struct device *dev)
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static inline void _extra_clock_on(struct device *dev)
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{
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const struct spi_dw_config *info = dev->config->config_info;
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set_bit_clk_ena(info->regs);
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}
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static inline void _clock_off(struct device *dev)
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static inline void _extra_clock_off(struct device *dev)
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{
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const struct spi_dw_config *info = dev->config->config_info;
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