From a7bda0896054c3ac043a2d5819612c478fd97a62 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Manuel=20Arg=C3=BCelles?= Date: Thu, 28 Sep 2023 16:38:12 +0700 Subject: [PATCH] nxp: s32ze: take exceptions in Arm mode MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cortex-R52 supports both Arm and Thumb-2 mode, but Zephyr's ASM code for Armv-8 Aarch32 is written for Arm mode only. This Soc has a general purpose register that can set the core TEINIT signal to change the mode exceptions are taken before booting up the core. The debugger startup scripts or firmware booting up the core may configure this bit to Thumb mode, as is the case of the NXP S32 debug probe startup scripts for S32ZE. Due to above reason, clear SCTLR.TE bit at reset so that TEINIT value is ignored and exceptions are always taken into Arm mode, compatible with current Zephyr ASM code. At least until taking execeptions in Thumb mode is supported in Zephyr. Signed-off-by: Manuel Argüelles --- soc/arm/nxp_s32/s32ze/soc.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/soc/arm/nxp_s32/s32ze/soc.c b/soc/arm/nxp_s32/s32ze/soc.c index 36acfbf9dc8..871536a26c6 100644 --- a/soc/arm/nxp_s32/s32ze/soc.c +++ b/soc/arm/nxp_s32/s32ze/soc.c @@ -21,6 +21,12 @@ void z_arm_platform_init(void) barrier_dsync_fence_full(); barrier_isync_fence_full(); + /* + * Take exceptions in Arm mode because Zephyr ASM code for Cortex-R Aarch32 + * is written for Arm + */ + __set_SCTLR(__get_SCTLR() & ~SCTLR_TE_Msk); + if (IS_ENABLED(CONFIG_ICACHE)) { if (!(__get_SCTLR() & SCTLR_I_Msk)) { L1C_InvalidateICacheAll();