diff --git a/dts/arm/Makefile b/dts/arm/Makefile
index 92f9b17cb4a..2fa6c240452 100644
--- a/dts/arm/Makefile
+++ b/dts/arm/Makefile
@@ -5,5 +5,6 @@ dtb-$(CONFIG_BOARD_HEXIWEAR_K64)	=	hexiwear_k64.dts_compiled
 dtb-$(CONFIG_BOARD_CC3200_LAUNCHXL)	=	cc3200_launchxl.dts_compiled
 dtb-$(CONFIG_BOARD_NUCLEO_L476RG)	=	nucleo_l476rg.dts_compiled
 dtb-$(CONFIG_BOARD_V2M_BEETLE)		=	v2m_beetle.dts_compiled
+dtb-$(CONFIG_BOARD_OLIMEXINO_STM32)	=	olimexino_stm32.dts_compiled
 always	:= $(dtb-y)
 endif
diff --git a/dts/arm/olimexino_stm32.dts b/dts/arm/olimexino_stm32.dts
new file mode 100644
index 00000000000..125ec2f0b24
--- /dev/null
+++ b/dts/arm/olimexino_stm32.dts
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2017 I-SENSE group of ICCS
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include "stm32f103xb.dtsi"
+
+/ {
+	model = "Olimex OLIMEXINO-STM32 board";
+	compatible = "st,olimexino_stm32", "st,stm32f103xb";
+
+	chosen {
+		zephyr,console = &usart1;
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		green {
+			gpios = <&gpioa 5 0>;
+		};
+		yellow {
+			gpios = <&gpioa 1 0>;
+		};
+	};
+};
+
+&clk_hse {
+	clock-frequency = <72000000>;
+};
+
+&usart1 {
+	status = "ok";
+};
diff --git a/dts/arm/olimexino_stm32.fixup b/dts/arm/olimexino_stm32.fixup
new file mode 100644
index 00000000000..4945ada58e9
--- /dev/null
+++ b/dts/arm/olimexino_stm32.fixup
@@ -0,0 +1,24 @@
+/* This file is a temporary workaround for mapping of the generated information
+ * to the current driver definitions.  This will be removed when the drivers
+ * are modified to handle the generated information, or the mapping of
+ * generated data matches the driver definitions.
+ */
+
+
+#define CONFIG_NUM_IRQS			ARM_ARMV7M_NVIC_E000E100_NUM_IRQS
+#define CONFIG_NUM_IRQ_PRIO_BITS	ARM_ARMV7M_NVIC_E000E100_NUM_IRQ_PRIO_BITS
+
+#define CONFIG_UART_STM32_PORT_1_BASE_ADDRESS	ST_STM32_USART_40013800_BASE_ADDRESS
+#define CONFIG_UART_STM32_PORT_1_BAUD_RATE	ST_STM32_USART_40013800_BAUD_RATE
+#define CONFIG_UART_STM32_PORT_1_IRQ_PRI	ST_STM32_USART_40013800_ZEPHYR_IRQ_PRIO
+#define PORT_1_IRQ				ST_STM32_USART_40013800_IRQ_0
+
+#define CONFIG_UART_STM32_PORT_2_BASE_ADDRESS	ST_STM32_USART_40004400_BASE_ADDRESS
+#define CONFIG_UART_STM32_PORT_2_BAUD_RATE	ST_STM32_USART_40004400_BAUD_RATE
+#define CONFIG_UART_STM32_PORT_2_IRQ_PRI	ST_STM32_USART_40004400_ZEPHYR_IRQ_PRIO
+#define PORT_2_IRQ				ST_STM32_USART_40004400_IRQ_0
+
+#define CONFIG_UART_STM32_PORT_3_BASE_ADDRESS	ST_STM32_USART_40004800_BASE_ADDRESS
+#define CONFIG_UART_STM32_PORT_3_BAUD_RATE	ST_STM32_USART_40004800_BAUD_RATE
+#define CONFIG_UART_STM32_PORT_3_IRQ_PRI	ST_STM32_USART_40004800_ZEPHYR_IRQ_PRIO
+#define PORT_3_IRQ				ST_STM32_USART_40004800_IRQ_0
diff --git a/dts/arm/stm32f103xb.dtsi b/dts/arm/stm32f103xb.dtsi
new file mode 100644
index 00000000000..4833441ff5d
--- /dev/null
+++ b/dts/arm/stm32f103xb.dtsi
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2017 I-SENSE group of ICCS
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "armv7-m.dtsi"
+
+/ {
+	sram0: memory {
+		reg = <0x20000000 0x5000>;
+	};
+
+	flash0: flash {
+		reg = <0x08000000 0x20000>;
+	};
+
+	clocks {
+		clk_hse: clk-hse {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <0>;
+		};
+	};
+
+	soc {
+		usart1: uart@40013800 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40013800 0x400>;
+			interrupts = <37>;
+			zephyr,irq-prio = <0>;
+			baud-rate = <115200>;
+			status = "disabled";
+		};
+
+		usart2: uart@40004400 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40004400 0x400>;
+			interrupts = <38>;
+			zephyr,irq-prio = <0>;
+			baud-rate = <115200>;
+			status = "disabled";
+		};
+
+		usart3: uart@40004800 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40004800 0x400>;
+			interrupts = <39>;
+			zephyr,irq-prio = <0>;
+			baud-rate = <115200>;
+			status = "disabled";
+		};
+
+		pin-controller {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "st,stm32f103xb-pinctrl";
+			ranges = <0 0x40010800 0x1400>;
+
+			gpioa: gpio@40010800 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x0 0x400>;
+				st,bank-name = "GPIOA";
+			};
+
+			gpiob: gpio@40010C00 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x400 0x400>;
+				st,bank-name = "GPIOB";
+			};
+
+			gpioc: gpio@40011000 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x800 0x400>;
+				st,bank-name = "GPIOC";
+			};
+
+			gpiod: gpio@40011400 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0xc00 0x400>;
+				st,bank-name = "GPIOD";
+			};
+
+			gpioe: gpio@40011800 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x1000 0x400>;
+				st,bank-name = "GPIOE";
+			};
+		};
+	};
+};
+
+&nvic {
+	num-irq-prio-bits = <4>;
+	num-irqs = <59>;
+};