drivers: pinctrl: rename S32 to NXP S32
Following updates previously done for other drivers, rename all occurrences of S32 to NXP S32 to avoid ambiguity. Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
This commit is contained in:
Manuel Arguelles
Carles Cufí
parent
415131c2e4
commit
a7743a49aa
8 changed files with 114 additions and 114 deletions
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@ -26,5 +26,5 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_RV32M1 pinctrl_rv32m1.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_XLNX_ZYNQ pinctrl_xlnx_zynq.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_SMARTBOND pinctrl_smartbond.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_XMC4XXX pinctrl_xmc4xxx.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_S32 pinctrl_s32.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_NXP_S32 pinctrl_nxp_s32.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_GECKO pinctrl_gecko.c)
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@ -55,7 +55,7 @@ source "drivers/pinctrl/Kconfig.rv32m1"
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source "drivers/pinctrl/Kconfig.xlnx"
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source "drivers/pinctrl/Kconfig.smartbond"
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source "drivers/pinctrl/Kconfig.xmc4xxx"
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source "drivers/pinctrl/Kconfig.s32"
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source "drivers/pinctrl/Kconfig.nxp_s32"
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source "drivers/pinctrl/Kconfig.gecko"
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endif # PINCTRL
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@ -1,7 +1,7 @@
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# Copyright 2022 NXP
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# SPDX-License-Identifier: Apache-2.0
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config PINCTRL_S32
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config PINCTRL_NXP_S32
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bool "Pin controller driver for NXP S32 processors"
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default y
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depends on DT_HAS_NXP_S32ZE_PINCTRL_ENABLED
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77
include/zephyr/dt-bindings/pinctrl/nxp-s32-pinctrl.h
Normal file
77
include/zephyr/dt-bindings/pinctrl/nxp-s32-pinctrl.h
Normal file
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@ -0,0 +1,77 @@
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/*
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* Copyright 2022 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_NXP_S32_PINCTRL_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_NXP_S32_PINCTRL_H_
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#include <zephyr/sys/util_macro.h>
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/*
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* The NXP S32 pinmux configuration is encoded in a 32-bit field value as follows:
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*
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* - 0..2: Output mux Source Signal Selection (MSCR.SSS)
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* - 3..6: Input mux Source Signal Selection (IMCR.SSS)
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* - 7..15: Input Multiplexed Signal Configuration Register (IMCR) index
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* - 16..24: Multiplexed Signal Configuration Register (MSCR) index
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* - 25..27: SIUL2 instance index (0..7)
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* - 28..31: Reserved for future use
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*/
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#define NXP_S32_MSCR_SSS_SHIFT 0U
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#define NXP_S32_MSCR_SSS_MASK BIT_MASK(3)
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#define NXP_S32_IMCR_SSS_SHIFT 3U
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#define NXP_S32_IMCR_SSS_MASK BIT_MASK(4)
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#define NXP_S32_IMCR_IDX_SHIFT 7U
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#define NXP_S32_IMCR_IDX_MASK BIT_MASK(9)
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#define NXP_S32_MSCR_IDX_SHIFT 16U
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#define NXP_S32_MSCR_IDX_MASK BIT_MASK(9)
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#define NXP_S32_SIUL2_IDX_SHIFT 25U
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#define NXP_S32_SIUL2_IDX_MASK BIT_MASK(3)
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#define NXP_S32_PINMUX_MSCR_SSS(cfg) \
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(((cfg) & NXP_S32_MSCR_SSS_MASK) << NXP_S32_MSCR_SSS_SHIFT)
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#define NXP_S32_PINMUX_IMCR_SSS(cfg) \
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(((cfg) & NXP_S32_IMCR_SSS_MASK) << NXP_S32_IMCR_SSS_SHIFT)
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#define NXP_S32_PINMUX_IMCR_IDX(cfg) \
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(((cfg) & NXP_S32_IMCR_IDX_MASK) << NXP_S32_IMCR_IDX_SHIFT)
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#define NXP_S32_PINMUX_MSCR_IDX(cfg) \
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(((cfg) & NXP_S32_MSCR_IDX_MASK) << NXP_S32_MSCR_IDX_SHIFT)
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#define NXP_S32_PINMUX_SIUL2_IDX(cfg) \
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(((cfg) & NXP_S32_SIUL2_IDX_MASK) << NXP_S32_SIUL2_IDX_SHIFT)
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#define NXP_S32_PINMUX_GET_MSCR_SSS(cfg) \
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(((cfg) >> NXP_S32_MSCR_SSS_SHIFT) & NXP_S32_MSCR_SSS_MASK)
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#define NXP_S32_PINMUX_GET_IMCR_SSS(cfg) \
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(((cfg) >> NXP_S32_IMCR_SSS_SHIFT) & NXP_S32_IMCR_SSS_MASK)
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#define NXP_S32_PINMUX_GET_IMCR_IDX(cfg) \
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(((cfg) >> NXP_S32_IMCR_IDX_SHIFT) & NXP_S32_IMCR_IDX_MASK)
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#define NXP_S32_PINMUX_GET_MSCR_IDX(cfg) \
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(((cfg) >> NXP_S32_MSCR_IDX_SHIFT) & NXP_S32_MSCR_IDX_MASK)
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#define NXP_S32_PINMUX_GET_SIUL2_IDX(cfg) \
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(((cfg) >> NXP_S32_SIUL2_IDX_SHIFT) & NXP_S32_SIUL2_IDX_MASK)
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/**
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* @brief Utility macro to build NXP S32 pinmux property for pinctrl nodes.
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*
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* @param siul2_idx SIUL2 instance index
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* @param mscr_idx Multiplexed Signal Configuration Register (MSCR) index
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* @param mscr_sss Output mux Source Signal Selection (MSCR.SSS)
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* @param imcr_idx Input Multiplexed Signal Configuration Register (IMCR) index
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* @param imcr_sss Input mux Source Signal Selection (IMCR.SSS)
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*/
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#define NXP_S32_PINMUX(siul2_idx, mscr_idx, mscr_sss, imcr_idx, imcr_sss) \
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(NXP_S32_PINMUX_SIUL2_IDX(siul2_idx) | NXP_S32_PINMUX_MSCR_IDX(mscr_idx) \
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| NXP_S32_PINMUX_MSCR_SSS(mscr_sss) | NXP_S32_PINMUX_IMCR_IDX(imcr_idx) \
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| NXP_S32_PINMUX_IMCR_SSS(imcr_sss))
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#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_NXP_NXP_S32_PINCTRL_H_ */
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@ -1,77 +0,0 @@
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/*
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* Copyright 2022 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_S32_PINCTRL_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_S32_PINCTRL_H_
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#include <zephyr/sys/util_macro.h>
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/*
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* The NXP S32 pinmux configuration is encoded in a 32-bit field value as follows:
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*
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* - 0..2: Output mux Source Signal Selection (MSCR.SSS)
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* - 3..6: Input mux Source Signal Selection (IMCR.SSS)
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* - 7..15: Input Multiplexed Signal Configuration Register (IMCR) index
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* - 16..24: Multiplexed Signal Configuration Register (MSCR) index
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* - 25..27: SIUL2 instance index (0..7)
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* - 28..31: Reserved for future use
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*/
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#define S32_MSCR_SSS_SHIFT 0U
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#define S32_MSCR_SSS_MASK BIT_MASK(3)
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#define S32_IMCR_SSS_SHIFT 3U
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#define S32_IMCR_SSS_MASK BIT_MASK(4)
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#define S32_IMCR_IDX_SHIFT 7U
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#define S32_IMCR_IDX_MASK BIT_MASK(9)
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#define S32_MSCR_IDX_SHIFT 16U
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#define S32_MSCR_IDX_MASK BIT_MASK(9)
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#define S32_SIUL2_IDX_SHIFT 25U
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#define S32_SIUL2_IDX_MASK BIT_MASK(3)
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#define S32_PINMUX_MSCR_SSS(cfg) \
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(((cfg) & S32_MSCR_SSS_MASK) << S32_MSCR_SSS_SHIFT)
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#define S32_PINMUX_IMCR_SSS(cfg) \
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(((cfg) & S32_IMCR_SSS_MASK) << S32_IMCR_SSS_SHIFT)
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#define S32_PINMUX_IMCR_IDX(cfg) \
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(((cfg) & S32_IMCR_IDX_MASK) << S32_IMCR_IDX_SHIFT)
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#define S32_PINMUX_MSCR_IDX(cfg) \
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(((cfg) & S32_MSCR_IDX_MASK) << S32_MSCR_IDX_SHIFT)
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#define S32_PINMUX_SIUL2_IDX(cfg) \
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(((cfg) & S32_SIUL2_IDX_MASK) << S32_SIUL2_IDX_SHIFT)
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#define S32_PINMUX_GET_MSCR_SSS(cfg) \
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(((cfg) >> S32_MSCR_SSS_SHIFT) & S32_MSCR_SSS_MASK)
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#define S32_PINMUX_GET_IMCR_SSS(cfg) \
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(((cfg) >> S32_IMCR_SSS_SHIFT) & S32_IMCR_SSS_MASK)
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#define S32_PINMUX_GET_IMCR_IDX(cfg) \
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(((cfg) >> S32_IMCR_IDX_SHIFT) & S32_IMCR_IDX_MASK)
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#define S32_PINMUX_GET_MSCR_IDX(cfg) \
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(((cfg) >> S32_MSCR_IDX_SHIFT) & S32_MSCR_IDX_MASK)
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#define S32_PINMUX_GET_SIUL2_IDX(cfg) \
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(((cfg) >> S32_SIUL2_IDX_SHIFT) & S32_SIUL2_IDX_MASK)
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/**
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* @brief Utility macro to build NXP S32 pinmux property for pinctrl nodes.
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*
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* @param siul2_idx SIUL2 instance index
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* @param mscr_idx Multiplexed Signal Configuration Register (MSCR) index
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* @param mscr_sss Output mux Source Signal Selection (MSCR.SSS)
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* @param imcr_idx Input Multiplexed Signal Configuration Register (IMCR) index
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* @param imcr_sss Input mux Source Signal Selection (IMCR.SSS)
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*/
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#define S32_PINMUX(siul2_idx, mscr_idx, mscr_sss, imcr_idx, imcr_sss) \
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(S32_PINMUX_SIUL2_IDX(siul2_idx) | S32_PINMUX_MSCR_IDX(mscr_idx) \
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| S32_PINMUX_MSCR_SSS(mscr_sss) | S32_PINMUX_IMCR_IDX(imcr_idx) \
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| S32_PINMUX_IMCR_SSS(imcr_sss))
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#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_S32_PINCTRL_H_ */
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@ -8,7 +8,7 @@
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#define ZEPHYR_SOC_ARM_NXP_S32_COMMON_PINCTRL_SOC_COMMON_H_
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#include <zephyr/devicetree.h>
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#include <zephyr/dt-bindings/pinctrl/s32-pinctrl.h>
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#include <zephyr/dt-bindings/pinctrl/nxp-s32-pinctrl.h>
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#include <zephyr/sys/util_macro.h>
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#include <zephyr/types.h>
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@ -22,11 +22,11 @@
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* Each SoC implementing Pinctrl must create a "pinctrl_soc.h" which includes
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* this file and defines the following macros:
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*
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* - S32_PIN_OPTIONS_INIT(group, mux)
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* - NXP_S32_PIN_OPTIONS_INIT(group, mux)
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* Populates SoC members of Siul2_Port_Ip_PinSettingsConfig struct based on
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* SoC-specific group properties and the pinmux configuration.
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*
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* - S32_SIUL2_IDX(n)
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* - NXP_S32_SIUL2_IDX(n)
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* Expands to the SIUL2 struct pointer for the instance "n". The number of
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* instances is SoC specific and may be not contiguous.
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* Note: "n" may be a preprocessor expression so cannot be concatenated.
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@ -35,40 +35,40 @@
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/** @brief Type for NXP S32 pin configuration. */
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typedef Siul2_Port_Ip_PinSettingsConfig pinctrl_soc_pin_t;
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#define S32_INPUT_BUFFER(group) \
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#define NXP_S32_INPUT_BUFFER(group) \
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COND_CODE_1(DT_PROP(group, input_enable), (PORT_INPUT_BUFFER_ENABLED), \
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(PORT_INPUT_BUFFER_DISABLED))
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#define S32_OUTPUT_BUFFER(group) \
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#define NXP_S32_OUTPUT_BUFFER(group) \
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COND_CODE_1(DT_PROP(group, output_enable), (PORT_OUTPUT_BUFFER_ENABLED),\
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(PORT_OUTPUT_BUFFER_DISABLED))
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#define S32_INPUT_MUX_REG(group, val) \
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COND_CODE_1(DT_PROP(group, input_enable), (S32_PINMUX_GET_IMCR_IDX(val)),\
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#define NXP_S32_INPUT_MUX_REG(group, val) \
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COND_CODE_1(DT_PROP(group, input_enable), (NXP_S32_PINMUX_GET_IMCR_IDX(val)), \
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(0U))
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#define S32_INPUT_MUX(group, val) \
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#define NXP_S32_INPUT_MUX(group, val) \
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COND_CODE_1(DT_PROP(group, input_enable), \
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((Siul2_Port_Ip_PortInputMux)S32_PINMUX_GET_IMCR_SSS(val)), \
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((Siul2_Port_Ip_PortInputMux)NXP_S32_PINMUX_GET_IMCR_SSS(val)), \
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(PORT_INPUT_MUX_NO_INIT))
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/* Only a single input mux is configured, the rest is not used */
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#define S32_INPUT_MUX_NO_INIT \
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#define NXP_S32_INPUT_MUX_NO_INIT \
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[1 ... (FEATURE_SIUL2_MAX_NUMBER_OF_INPUT-1)] = PORT_INPUT_MUX_NO_INIT
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#define S32_PINMUX_INIT(group, val) \
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.base = S32_SIUL2_IDX(S32_PINMUX_GET_SIUL2_IDX(val)), \
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.pinPortIdx = S32_PINMUX_GET_MSCR_IDX(val), \
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.mux = (Siul2_Port_Ip_PortMux)S32_PINMUX_GET_MSCR_SSS(val), \
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#define NXP_S32_PINMUX_INIT(group, val) \
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.base = NXP_S32_SIUL2_IDX(NXP_S32_PINMUX_GET_SIUL2_IDX(val)), \
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.pinPortIdx = NXP_S32_PINMUX_GET_MSCR_IDX(val), \
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.mux = (Siul2_Port_Ip_PortMux)NXP_S32_PINMUX_GET_MSCR_SSS(val), \
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.inputMux = { \
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S32_INPUT_MUX(group, val), \
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S32_INPUT_MUX_NO_INIT \
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NXP_S32_INPUT_MUX(group, val), \
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NXP_S32_INPUT_MUX_NO_INIT \
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}, \
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.inputMuxReg = { \
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S32_INPUT_MUX_REG(group, val) \
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NXP_S32_INPUT_MUX_REG(group, val) \
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}, \
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.inputBuffer = S32_INPUT_BUFFER(group), \
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.outputBuffer = S32_OUTPUT_BUFFER(group),
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.inputBuffer = NXP_S32_INPUT_BUFFER(group), \
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.outputBuffer = NXP_S32_OUTPUT_BUFFER(group),
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/**
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* @brief Utility macro to initialize each pin.
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@ -80,8 +80,8 @@ typedef Siul2_Port_Ip_PinSettingsConfig pinctrl_soc_pin_t;
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*/
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#define Z_PINCTRL_STATE_PIN_INIT(group, prop, idx) \
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{ \
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S32_PINMUX_INIT(group, DT_PROP_BY_IDX(group, prop, idx)) \
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S32_PIN_OPTIONS_INIT(group, DT_PROP_BY_IDX(group, prop, idx)) \
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NXP_S32_PINMUX_INIT(group, DT_PROP_BY_IDX(group, prop, idx)) \
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NXP_S32_PIN_OPTIONS_INIT(group, DT_PROP_BY_IDX(group, prop, idx)) \
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},
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/**
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@ -97,4 +97,4 @@ typedef Siul2_Port_Ip_PinSettingsConfig pinctrl_soc_pin_t;
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/** @endcond */
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#endif /* ZEPHYR_SOC_ARM_NXP_S32_COMMON_PINCTRL_SOC_COMMON_H_ */
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#endif /* ZEPHYR_SOC_ARM_NXP_NXP_S32_COMMON_PINCTRL_SOC_COMMON_H_ */
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#error "SoC not supported"
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#endif
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#define S32_SIUL2_IDX(n) \
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#define NXP_S32_SIUL2_IDX(n) \
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n == 0 ? IP_SIUL2_0 : (n == 1 ? IP_SIUL2_1 : ( \
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n == 3 ? IP_SIUL2_3 : (n == 4 ? IP_SIUL2_4 : ( \
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n == 5 ? IP_SIUL2_5 : (NULL)))))
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#define S32_PULL_SEL(group) \
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COND_CODE_1(DT_PROP(group, bias_pull_up), (PORT_INTERNAL_PULL_UP_ENABLED),\
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#define NXP_S32_PULL_SEL(group) \
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COND_CODE_1(DT_PROP(group, bias_pull_up), (PORT_INTERNAL_PULL_UP_ENABLED), \
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(COND_CODE_1(DT_PROP(group, bias_pull_down), \
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(PORT_INTERNAL_PULL_DOWN_ENABLED), (PORT_INTERNAL_PULL_NOT_ENABLED))))
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/* To enable open drain both OBE and ODE bits need to be set */
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#define S32_OPEN_DRAIN(group) \
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#define NXP_S32_OPEN_DRAIN(group) \
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DT_PROP(group, drive_open_drain) && DT_PROP(group, output_enable) ? \
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(PORT_OPEN_DRAIN_ENABLED) : (PORT_OPEN_DRAIN_DISABLED)
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#define S32_SLEW_RATE(group) \
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#define NXP_S32_SLEW_RATE(group) \
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COND_CODE_1(DT_NODE_HAS_PROP(group, slew_rate), \
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(UTIL_CAT(PORT_SLEW_RATE_CONTROL, DT_PROP(group, slew_rate))), \
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(PORT_SLEW_RATE_CONTROL0))
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@ -39,10 +39,10 @@
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* The default values are reset values and don't apply to the type of pads
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* currently supported.
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*/
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#define S32_PIN_OPTIONS_INIT(group, mux) \
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.pullConfig = S32_PULL_SEL(group), \
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.openDrain = S32_OPEN_DRAIN(group), \
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.slewRateCtrlSel = S32_SLEW_RATE(group), \
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#define NXP_S32_PIN_OPTIONS_INIT(group, mux) \
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.pullConfig = NXP_S32_PULL_SEL(group), \
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.openDrain = NXP_S32_OPEN_DRAIN(group), \
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.slewRateCtrlSel = NXP_S32_SLEW_RATE(group), \
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.terminationResistor = PORT_TERMINATION_RESISTOR_DISABLED, \
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.receiverSel = PORT_RECEIVER_ENABLE_SINGLE_ENDED, \
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.currentReferenceControl = PORT_CURRENT_REFERENCE_CONTROL_DISABLED, \
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