drivers: pinctrl: rename S32 to NXP S32

Following updates previously done for other drivers, rename all
occurrences of S32 to NXP S32 to avoid ambiguity.

Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>

drivers/pinctrl/CMakeLists.txt

@@ -26,5 +26,5 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_RV32M1 pinctrl_rv32m1.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_XLNX_ZYNQ pinctrl_xlnx_zynq.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_SMARTBOND pinctrl_smartbond.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_XMC4XXX pinctrl_xmc4xxx.c)
-zephyr_library_sources_ifdef(CONFIG_PINCTRL_S32 pinctrl_s32.c)
+zephyr_library_sources_ifdef(CONFIG_PINCTRL_NXP_S32 pinctrl_nxp_s32.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_GECKO pinctrl_gecko.c)

drivers/pinctrl/Kconfig

@@ -55,7 +55,7 @@ source "drivers/pinctrl/Kconfig.rv32m1"
 source "drivers/pinctrl/Kconfig.xlnx"
 source "drivers/pinctrl/Kconfig.smartbond"
 source "drivers/pinctrl/Kconfig.xmc4xxx"
-source "drivers/pinctrl/Kconfig.s32"
+source "drivers/pinctrl/Kconfig.nxp_s32"
 source "drivers/pinctrl/Kconfig.gecko"
 
 endif # PINCTRL

drivers/pinctrl/Kconfig.nxp_s32

@@ -1,7 +1,7 @@
 # Copyright 2022 NXP
 # SPDX-License-Identifier: Apache-2.0
 
-config PINCTRL_S32
+config PINCTRL_NXP_S32
 	bool "Pin controller driver for NXP S32 processors"
 	default y
 	depends on DT_HAS_NXP_S32ZE_PINCTRL_ENABLED

include/zephyr/dt-bindings/pinctrl/nxp-s32-pinctrl.h

@@ -0,0 +1,77 @@
+/*
+ * Copyright 2022 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_NXP_S32_PINCTRL_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_NXP_S32_PINCTRL_H_
+
+#include <zephyr/sys/util_macro.h>
+
+/*
+ * The NXP S32 pinmux configuration is encoded in a 32-bit field value as follows:
+ *
+ * - 0..2:   Output mux Source Signal Selection (MSCR.SSS)
+ * - 3..6:   Input mux Source Signal Selection (IMCR.SSS)
+ * - 7..15:  Input Multiplexed Signal Configuration Register (IMCR) index
+ * - 16..24: Multiplexed Signal Configuration Register (MSCR) index
+ * - 25..27: SIUL2 instance index (0..7)
+ * - 28..31: Reserved for future use
+ */
+#define NXP_S32_MSCR_SSS_SHIFT	0U
+#define NXP_S32_MSCR_SSS_MASK	BIT_MASK(3)
+#define NXP_S32_IMCR_SSS_SHIFT	3U
+#define NXP_S32_IMCR_SSS_MASK	BIT_MASK(4)
+#define NXP_S32_IMCR_IDX_SHIFT	7U
+#define NXP_S32_IMCR_IDX_MASK	BIT_MASK(9)
+#define NXP_S32_MSCR_IDX_SHIFT	16U
+#define NXP_S32_MSCR_IDX_MASK	BIT_MASK(9)
+#define NXP_S32_SIUL2_IDX_SHIFT	25U
+#define NXP_S32_SIUL2_IDX_MASK	BIT_MASK(3)
+
+#define NXP_S32_PINMUX_MSCR_SSS(cfg)	\
+	(((cfg) & NXP_S32_MSCR_SSS_MASK) << NXP_S32_MSCR_SSS_SHIFT)
+
+#define NXP_S32_PINMUX_IMCR_SSS(cfg)	\
+	(((cfg) & NXP_S32_IMCR_SSS_MASK) << NXP_S32_IMCR_SSS_SHIFT)
+
+#define NXP_S32_PINMUX_IMCR_IDX(cfg)	\
+	(((cfg) & NXP_S32_IMCR_IDX_MASK) << NXP_S32_IMCR_IDX_SHIFT)
+
+#define NXP_S32_PINMUX_MSCR_IDX(cfg)	\
+	(((cfg) & NXP_S32_MSCR_IDX_MASK) << NXP_S32_MSCR_IDX_SHIFT)
+
+#define NXP_S32_PINMUX_SIUL2_IDX(cfg)	\
+	(((cfg) & NXP_S32_SIUL2_IDX_MASK) << NXP_S32_SIUL2_IDX_SHIFT)
+
+#define NXP_S32_PINMUX_GET_MSCR_SSS(cfg)	\
+	(((cfg) >> NXP_S32_MSCR_SSS_SHIFT) & NXP_S32_MSCR_SSS_MASK)
+
+#define NXP_S32_PINMUX_GET_IMCR_SSS(cfg)	\
+	(((cfg) >> NXP_S32_IMCR_SSS_SHIFT) & NXP_S32_IMCR_SSS_MASK)
+
+#define NXP_S32_PINMUX_GET_IMCR_IDX(cfg)	\
+	(((cfg) >> NXP_S32_IMCR_IDX_SHIFT) & NXP_S32_IMCR_IDX_MASK)
+
+#define NXP_S32_PINMUX_GET_MSCR_IDX(cfg)	\
+	(((cfg) >> NXP_S32_MSCR_IDX_SHIFT) & NXP_S32_MSCR_IDX_MASK)
+
+#define NXP_S32_PINMUX_GET_SIUL2_IDX(cfg)	\
+	(((cfg) >> NXP_S32_SIUL2_IDX_SHIFT) & NXP_S32_SIUL2_IDX_MASK)
+
+/**
+ * @brief Utility macro to build NXP S32 pinmux property for pinctrl nodes.
+ *
+ * @param siul2_idx SIUL2 instance index
+ * @param mscr_idx Multiplexed Signal Configuration Register (MSCR) index
+ * @param mscr_sss Output mux Source Signal Selection (MSCR.SSS)
+ * @param imcr_idx Input Multiplexed Signal Configuration Register (IMCR) index
+ * @param imcr_sss Input mux Source Signal Selection (IMCR.SSS)
+ */
+#define NXP_S32_PINMUX(siul2_idx, mscr_idx, mscr_sss, imcr_idx, imcr_sss)		\
+	(NXP_S32_PINMUX_SIUL2_IDX(siul2_idx) | NXP_S32_PINMUX_MSCR_IDX(mscr_idx)	\
+	 | NXP_S32_PINMUX_MSCR_SSS(mscr_sss) | NXP_S32_PINMUX_IMCR_IDX(imcr_idx)	\
+	 | NXP_S32_PINMUX_IMCR_SSS(imcr_sss))
+
+#endif	/* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_NXP_NXP_S32_PINCTRL_H_ */

include/zephyr/dt-bindings/pinctrl/s32-pinctrl.h

@@ -1,77 +0,0 @@
-/*
- * Copyright 2022 NXP
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_S32_PINCTRL_H_
-#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_S32_PINCTRL_H_
-
-#include <zephyr/sys/util_macro.h>
-
-/*
- * The NXP S32 pinmux configuration is encoded in a 32-bit field value as follows:
- *
- * - 0..2:   Output mux Source Signal Selection (MSCR.SSS)
- * - 3..6:   Input mux Source Signal Selection (IMCR.SSS)
- * - 7..15:  Input Multiplexed Signal Configuration Register (IMCR) index
- * - 16..24: Multiplexed Signal Configuration Register (MSCR) index
- * - 25..27: SIUL2 instance index (0..7)
- * - 28..31: Reserved for future use
- */
-#define S32_MSCR_SSS_SHIFT	0U
-#define S32_MSCR_SSS_MASK	BIT_MASK(3)
-#define S32_IMCR_SSS_SHIFT	3U
-#define S32_IMCR_SSS_MASK	BIT_MASK(4)
-#define S32_IMCR_IDX_SHIFT	7U
-#define S32_IMCR_IDX_MASK	BIT_MASK(9)
-#define S32_MSCR_IDX_SHIFT	16U
-#define S32_MSCR_IDX_MASK	BIT_MASK(9)
-#define S32_SIUL2_IDX_SHIFT	25U
-#define S32_SIUL2_IDX_MASK	BIT_MASK(3)
-
-#define S32_PINMUX_MSCR_SSS(cfg)	\
-	(((cfg) & S32_MSCR_SSS_MASK) << S32_MSCR_SSS_SHIFT)
-
-#define S32_PINMUX_IMCR_SSS(cfg)	\
-	(((cfg) & S32_IMCR_SSS_MASK) << S32_IMCR_SSS_SHIFT)
-
-#define S32_PINMUX_IMCR_IDX(cfg)	\
-	(((cfg) & S32_IMCR_IDX_MASK) << S32_IMCR_IDX_SHIFT)
-
-#define S32_PINMUX_MSCR_IDX(cfg)	\
-	(((cfg) & S32_MSCR_IDX_MASK) << S32_MSCR_IDX_SHIFT)
-
-#define S32_PINMUX_SIUL2_IDX(cfg)	\
-	(((cfg) & S32_SIUL2_IDX_MASK) << S32_SIUL2_IDX_SHIFT)
-
-#define S32_PINMUX_GET_MSCR_SSS(cfg)	\
-	(((cfg) >> S32_MSCR_SSS_SHIFT) & S32_MSCR_SSS_MASK)
-
-#define S32_PINMUX_GET_IMCR_SSS(cfg)	\
-	(((cfg) >> S32_IMCR_SSS_SHIFT) & S32_IMCR_SSS_MASK)
-
-#define S32_PINMUX_GET_IMCR_IDX(cfg)	\
-	(((cfg) >> S32_IMCR_IDX_SHIFT) & S32_IMCR_IDX_MASK)
-
-#define S32_PINMUX_GET_MSCR_IDX(cfg)	\
-	(((cfg) >> S32_MSCR_IDX_SHIFT) & S32_MSCR_IDX_MASK)
-
-#define S32_PINMUX_GET_SIUL2_IDX(cfg)	\
-	(((cfg) >> S32_SIUL2_IDX_SHIFT) & S32_SIUL2_IDX_MASK)
-
-/**
- * @brief Utility macro to build NXP S32 pinmux property for pinctrl nodes.
- *
- * @param siul2_idx SIUL2 instance index
- * @param mscr_idx Multiplexed Signal Configuration Register (MSCR) index
- * @param mscr_sss Output mux Source Signal Selection (MSCR.SSS)
- * @param imcr_idx Input Multiplexed Signal Configuration Register (IMCR) index
- * @param imcr_sss Input mux Source Signal Selection (IMCR.SSS)
- */
-#define S32_PINMUX(siul2_idx, mscr_idx, mscr_sss, imcr_idx, imcr_sss)		\
-	(S32_PINMUX_SIUL2_IDX(siul2_idx) | S32_PINMUX_MSCR_IDX(mscr_idx)	\
-	 | S32_PINMUX_MSCR_SSS(mscr_sss) | S32_PINMUX_IMCR_IDX(imcr_idx)	\
-	 | S32_PINMUX_IMCR_SSS(imcr_sss))
-
-#endif	/* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_S32_PINCTRL_H_ */

soc/arm/nxp_s32/common/pinctrl_soc_common.h

@@ -8,7 +8,7 @@
 #define ZEPHYR_SOC_ARM_NXP_S32_COMMON_PINCTRL_SOC_COMMON_H_
 
 #include <zephyr/devicetree.h>
-#include <zephyr/dt-bindings/pinctrl/s32-pinctrl.h>
+#include <zephyr/dt-bindings/pinctrl/nxp-s32-pinctrl.h>
 #include <zephyr/sys/util_macro.h>
 #include <zephyr/types.h>
 
@@ -22,11 +22,11 @@
  * Each SoC implementing Pinctrl must create a "pinctrl_soc.h" which includes
  * this file and defines the following macros:
  *
- * - S32_PIN_OPTIONS_INIT(group, mux)
+ * - NXP_S32_PIN_OPTIONS_INIT(group, mux)
  *   Populates SoC members of Siul2_Port_Ip_PinSettingsConfig struct based on
  *   SoC-specific group properties and the pinmux configuration.
  *
- * - S32_SIUL2_IDX(n)
+ * - NXP_S32_SIUL2_IDX(n)
  *   Expands to the SIUL2 struct pointer for the instance "n". The number of
  *   instances is SoC specific and may be not contiguous.
  *   Note: "n" may be a preprocessor expression so cannot be concatenated.
@@ -35,40 +35,40 @@
 /** @brief Type for NXP S32 pin configuration. */
 typedef Siul2_Port_Ip_PinSettingsConfig pinctrl_soc_pin_t;
 
-#define S32_INPUT_BUFFER(group)							\
+#define NXP_S32_INPUT_BUFFER(group)						\
 	COND_CODE_1(DT_PROP(group, input_enable), (PORT_INPUT_BUFFER_ENABLED),	\
 		(PORT_INPUT_BUFFER_DISABLED))
 
-#define S32_OUTPUT_BUFFER(group)						\
+#define NXP_S32_OUTPUT_BUFFER(group)						\
 	COND_CODE_1(DT_PROP(group, output_enable), (PORT_OUTPUT_BUFFER_ENABLED),\
 		(PORT_OUTPUT_BUFFER_DISABLED))
 
-#define S32_INPUT_MUX_REG(group, val)						\
+#define NXP_S32_INPUT_MUX_REG(group, val)						\
-	COND_CODE_1(DT_PROP(group, input_enable), (S32_PINMUX_GET_IMCR_IDX(val)),\
+	COND_CODE_1(DT_PROP(group, input_enable), (NXP_S32_PINMUX_GET_IMCR_IDX(val)),	\
 		(0U))
 
-#define S32_INPUT_MUX(group, val)						\
+#define NXP_S32_INPUT_MUX(group, val)						\
 	COND_CODE_1(DT_PROP(group, input_enable),				\
-		((Siul2_Port_Ip_PortInputMux)S32_PINMUX_GET_IMCR_SSS(val)),	\
+		((Siul2_Port_Ip_PortInputMux)NXP_S32_PINMUX_GET_IMCR_SSS(val)),	\
 		(PORT_INPUT_MUX_NO_INIT))
 
 /* Only a single input mux is configured, the rest is not used */
-#define S32_INPUT_MUX_NO_INIT							\
+#define NXP_S32_INPUT_MUX_NO_INIT						\
 	[1 ... (FEATURE_SIUL2_MAX_NUMBER_OF_INPUT-1)] = PORT_INPUT_MUX_NO_INIT
 
-#define S32_PINMUX_INIT(group, val)						\
+#define NXP_S32_PINMUX_INIT(group, val)						\
-	.base = S32_SIUL2_IDX(S32_PINMUX_GET_SIUL2_IDX(val)),			\
+	.base = NXP_S32_SIUL2_IDX(NXP_S32_PINMUX_GET_SIUL2_IDX(val)),		\
-	.pinPortIdx = S32_PINMUX_GET_MSCR_IDX(val),				\
+	.pinPortIdx = NXP_S32_PINMUX_GET_MSCR_IDX(val),				\
-	.mux = (Siul2_Port_Ip_PortMux)S32_PINMUX_GET_MSCR_SSS(val),		\
+	.mux = (Siul2_Port_Ip_PortMux)NXP_S32_PINMUX_GET_MSCR_SSS(val),		\
 	.inputMux = {								\
-		S32_INPUT_MUX(group, val),					\
+		NXP_S32_INPUT_MUX(group, val),					\
-		S32_INPUT_MUX_NO_INIT						\
+		NXP_S32_INPUT_MUX_NO_INIT					\
 	},									\
 	.inputMuxReg = {							\
-		S32_INPUT_MUX_REG(group, val)					\
+		NXP_S32_INPUT_MUX_REG(group, val)				\
 	},									\
-	.inputBuffer = S32_INPUT_BUFFER(group),					\
+	.inputBuffer = NXP_S32_INPUT_BUFFER(group),				\
-	.outputBuffer = S32_OUTPUT_BUFFER(group),
+	.outputBuffer = NXP_S32_OUTPUT_BUFFER(group),
 
 /**
  * @brief Utility macro to initialize each pin.
@@ -80,8 +80,8 @@ typedef Siul2_Port_Ip_PinSettingsConfig pinctrl_soc_pin_t;
  */
 #define Z_PINCTRL_STATE_PIN_INIT(group, prop, idx)					\
 	{										\
-		S32_PINMUX_INIT(group, DT_PROP_BY_IDX(group, prop, idx))	\
+		NXP_S32_PINMUX_INIT(group, DT_PROP_BY_IDX(group, prop, idx))		\
-		S32_PIN_OPTIONS_INIT(group, DT_PROP_BY_IDX(group, prop, idx))	\
+		NXP_S32_PIN_OPTIONS_INIT(group, DT_PROP_BY_IDX(group, prop, idx))	\
 	},
 
 /**
@@ -97,4 +97,4 @@ typedef Siul2_Port_Ip_PinSettingsConfig pinctrl_soc_pin_t;
 
 /** @endcond */
 
-#endif /* ZEPHYR_SOC_ARM_NXP_S32_COMMON_PINCTRL_SOC_COMMON_H_ */
+#endif /* ZEPHYR_SOC_ARM_NXP_NXP_S32_COMMON_PINCTRL_SOC_COMMON_H_ */

soc/arm/nxp_s32/s32ze/pinctrl_soc.h

@@ -15,22 +15,22 @@
 #error "SoC not supported"
 #endif
 
-#define S32_SIUL2_IDX(n)							\
+#define NXP_S32_SIUL2_IDX(n)							\
 	n == 0 ? IP_SIUL2_0 : (n == 1 ? IP_SIUL2_1 : (				\
 	n == 3 ? IP_SIUL2_3 : (n == 4 ? IP_SIUL2_4 : (				\
 	n == 5 ? IP_SIUL2_5 : (NULL)))))
 
-#define S32_PULL_SEL(group)							\
+#define NXP_S32_PULL_SEL(group)								\
 	COND_CODE_1(DT_PROP(group, bias_pull_up), (PORT_INTERNAL_PULL_UP_ENABLED),	\
 		(COND_CODE_1(DT_PROP(group, bias_pull_down),				\
 		(PORT_INTERNAL_PULL_DOWN_ENABLED), (PORT_INTERNAL_PULL_NOT_ENABLED))))
 
 /* To enable open drain both OBE and ODE bits need to be set */
-#define S32_OPEN_DRAIN(group)							\
+#define NXP_S32_OPEN_DRAIN(group)						\
 	DT_PROP(group, drive_open_drain) && DT_PROP(group, output_enable) ?	\
 		(PORT_OPEN_DRAIN_ENABLED) : (PORT_OPEN_DRAIN_DISABLED)
 
-#define S32_SLEW_RATE(group)							\
+#define NXP_S32_SLEW_RATE(group)						\
 	COND_CODE_1(DT_NODE_HAS_PROP(group, slew_rate),				\
 		(UTIL_CAT(PORT_SLEW_RATE_CONTROL, DT_PROP(group, slew_rate))),	\
 		(PORT_SLEW_RATE_CONTROL0))
@@ -39,10 +39,10 @@
  * The default values are reset values and don't apply to the type of pads
  * currently supported.
  */
-#define S32_PIN_OPTIONS_INIT(group, mux)					\
+#define NXP_S32_PIN_OPTIONS_INIT(group, mux)					\
-	.pullConfig = S32_PULL_SEL(group),					\
+	.pullConfig = NXP_S32_PULL_SEL(group),					\
-	.openDrain = S32_OPEN_DRAIN(group),					\
+	.openDrain = NXP_S32_OPEN_DRAIN(group),					\
-	.slewRateCtrlSel = S32_SLEW_RATE(group),				\
+	.slewRateCtrlSel = NXP_S32_SLEW_RATE(group),				\
 	.terminationResistor = PORT_TERMINATION_RESISTOR_DISABLED,		\
 	.receiverSel = PORT_RECEIVER_ENABLE_SINGLE_ENDED,			\
 	.currentReferenceControl = PORT_CURRENT_REFERENCE_CONTROL_DISABLED,	\