diff --git a/boards/arm64/intel_socfpga_agilex_socdk/Kconfig.board b/boards/arm64/intel_socfpga_agilex_socdk/Kconfig.board new file mode 100644 index 00000000000..7dcc7b1e7a5 --- /dev/null +++ b/boards/arm64/intel_socfpga_agilex_socdk/Kconfig.board @@ -0,0 +1,6 @@ +# Copyright (c) 2021 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_INTEL_SOCFPGA_AGILEX_SOCDK + bool "Intel SoC FPGA Development Kit (Agilex)" + depends on SOC_AGILEX diff --git a/boards/arm64/intel_socfpga_agilex_socdk/Kconfig.defconfig b/boards/arm64/intel_socfpga_agilex_socdk/Kconfig.defconfig new file mode 100644 index 00000000000..58c3bddb5a1 --- /dev/null +++ b/boards/arm64/intel_socfpga_agilex_socdk/Kconfig.defconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2021 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD + default "intel_socfpga_agilex_socdk" + depends on BOARD_INTEL_SOCFPGA_AGILEX_SOCDK diff --git a/boards/arm64/intel_socfpga_agilex_socdk/doc/index.rst b/boards/arm64/intel_socfpga_agilex_socdk/doc/index.rst new file mode 100644 index 00000000000..93d38d91f74 --- /dev/null +++ b/boards/arm64/intel_socfpga_agilex_socdk/doc/index.rst @@ -0,0 +1,79 @@ +.. _intel_socfpga_agilex_socdk: + +Intel Agilex SoC Development Kit +################################# + +Overview +******** + +The Intel Agilex SoC Development Kit offers a complete design environment +that includes both hardware and software for developing Intel Agilex +F-Series FPGA designs. This kit is recommended for developing custom +Arm* processor-based SoC designs and evaluating transceiver performance. + +Hardware +******** + +The Intel Agilex SoC Development Kit supports the following physical features: + +- Intel Agilex F-Series FPGA, 1400 KLE, 2486A package integrate the + quad-core Arm Cortex-A53 processor +- On-board 8 GB DDR4 memory +- On-board JTAG Intel FPGA Download Cable II +- QSPI flash daughtercard +- HPS OOBE daughtercard with UART and SD Card support + +Supported Features +================== +The Intel Agilex SoC Development Kit configuration supports the following +hardware features: + ++-----------+------------+--------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================================+ +| GIC-400 | on-chip | GICv2 interrupt controller | ++-----------+------------+--------------------------------------+ +| ARM TIMER | on-chip | System Clock | ++-----------+------------+--------------------------------------+ +| UART | on-chip | NS16550 compatible serial port | ++-----------+------------+--------------------------------------+ + +Other hardware features are not supported by the Zephyr kernel. + +The default configuration can be found in the defconfig file: + + ``boards/arm64/intel_socfpga_agilex_socdk/intel_socfpga_agilex_socdk_defconfig`` + +Programming and Debugging +************************* + +Boot Flow +========= +Zephyr image will need to be loaded by Intel Arm Trusted Firmware (ATF). +ATF BL2 is first stage boot loader (FSBL) and ATF BL31 is second stage +boot loader (SSBL). + +Zephyr boot flow: + + ATF BL2 (EL3) -> ATF BL31 (EL3) -> Zephyr (EL2->EL1) + +Intel Arm Trusted Firmware (ATF) can be downloaded from github: + + `altera-opensource/arm-trusted-firmware `_ + +Flashing +======== +Zephyr image can be loaded in DDR memory at address 0x10000000 from +SD Card or QSPI Flash in ATF BL2. + +Debugging +========= +The Intel Agilex SoC Development Kit includes one JTAG connector on +board, connect it to Intel USB blaster download cables for debugging. + +Zephyr applications running on the Cortex-A53 core can be tested by +observing UART console output. + +References +========== +`Intel Agilex Transceiver-SoC Development Kit `_ diff --git a/boards/arm64/intel_socfpga_agilex_socdk/intel_socfpga_agilex_socdk.dts b/boards/arm64/intel_socfpga_agilex_socdk/intel_socfpga_agilex_socdk.dts new file mode 100644 index 00000000000..66d392e5d29 --- /dev/null +++ b/boards/arm64/intel_socfpga_agilex_socdk/intel_socfpga_agilex_socdk.dts @@ -0,0 +1,29 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (C) 2021, Intel Corporation + * + */ + +/dts-v1/; + +#include + +/ { + model = "Intel SoC FPGA Agilex"; + compatible = "intel,socfpga-agilex"; + #address-cells = <1>; + #size-cells = <1>; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,sram = &mem0; + }; + +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; +}; diff --git a/boards/arm64/intel_socfpga_agilex_socdk/intel_socfpga_agilex_socdk.yaml b/boards/arm64/intel_socfpga_agilex_socdk/intel_socfpga_agilex_socdk.yaml new file mode 100644 index 00000000000..775ab2774de --- /dev/null +++ b/boards/arm64/intel_socfpga_agilex_socdk/intel_socfpga_agilex_socdk.yaml @@ -0,0 +1,7 @@ +identifier: intel_socfpga_agilex_socdk +name: Intel SoC FPGA Agilex +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile diff --git a/boards/arm64/intel_socfpga_agilex_socdk/intel_socfpga_agilex_socdk_defconfig b/boards/arm64/intel_socfpga_agilex_socdk/intel_socfpga_agilex_socdk_defconfig new file mode 100644 index 00000000000..de7b626abbb --- /dev/null +++ b/boards/arm64/intel_socfpga_agilex_socdk/intel_socfpga_agilex_socdk_defconfig @@ -0,0 +1,27 @@ +# Copyright (c) 2021 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +# The Zephyr build from this defconfig is execpted to boot from +# Intel Arm Trusted Firmware (ATF) +# Boot Flow: BL21 -> BL31 -> Zephyr + +CONFIG_SOC_SERIES_AGILEX=y +CONFIG_SOC_AGILEX=y +CONFIG_BOARD_INTEL_SOCFPGA_AGILEX_SOCDK=y +CONFIG_ARM_ARCH_TIMER=y + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_NS16550=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_UART_NS16550_ACCESS_WORD_ONLY=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable Clock Manager +CONFIG_CLOCK_CONTROL=y + +# For Misc Register Map +CONFIG_SYSCON=y