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riscv: use standard MSTATUS

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This is no longer needed, since all in-tree platforms are only using
the standard mstatus formats. Remove it to avoid the complexity.

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2020-01-03 18:18:24 -08:00 • committed by Anas Nashif
commit a6b3b616f5
11 changed files with 34 additions and 79 deletions
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22
soc/riscv/openisa_rv32m1/soc_ri5cy.h
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@ -49,13 +49,6 @@
* Some of these may also apply to ZERO-RISCY; needs investigation.
*/
/*
* MSTATUS CSR number. (Note this is the standard value in the RISC-V
* privileged ISA v1.10).
*/
#define SOC_MSTATUS_REG RI5CY_MSTATUS
/* MSTATUS's interrupt enable mask. This is also standard. */
#define SOC_MSTATUS_IEN (1U << 3)
/*
* Exception code mask. Use of the bottom five bits is a subset of
* what the standard allocates (which is XLEN-1 bits).
@ -70,19 +63,4 @@
#define SOC_ERET mret
/* The ecall exception number. This is a standard value. */
#define SOC_MCAUSE_ECALL_EXP 11
/*
* Default MSTATUS value to write when scheduling in a new thread for
* the first time.
*
* - Preserve machine privileges in MPP. If you see any documentation
* telling you that MPP is read-only on this SoC, don't believe its
* lies.
* - Enable interrupts when exiting from exception into a new thread
* by setting MPIE now, so it will be copied into IE on mret.
*/
#define RI5CY_MSTATUS_MPP_M (0x3U << 11)
#define RI5CY_MSTATUS_MPIE_EN (1U << 7)
#define SOC_MSTATUS_DEF_RESTORE (RI5CY_MSTATUS_MPP_M | \
RI5CY_MSTATUS_MPIE_EN)
#endif /* SOC_RISCV32_OPENISA_RV32M1_SOC_RI5CY_H_ */