boards: frdm_mcxn947: Add USBHS support

Add support for the USBHS controller

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>

boards/nxp/frdm_mcxn947/board.c

@@ -8,6 +8,15 @@
 #include <fsl_clock.h>
 #include <fsl_spc.h>
 #include <soc.h>
+#if CONFIG_USB_DC_NXP_EHCI
+#include "usb_phy.h"
+#include "usb.h"
+
+/* USB PHY condfiguration */
+#define BOARD_USB_PHY_D_CAL     (0x04U)
+#define BOARD_USB_PHY_TXCAL45DP (0x07U)
+#define BOARD_USB_PHY_TXCAL45DM (0x07U)
+#endif
 
 /* Board xtal frequency in Hz */
 #define BOARD_XTAL0_CLK_HZ                        24000000U
@@ -95,6 +104,8 @@ static int frdm_mcxn947_init(void)
 	/* Set AHBCLKDIV divider to value 1 */
 	CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);
 
+	CLOCK_SetupExtClocking(BOARD_XTAL0_CLK_HZ);
+
 #if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm1), okay)
 	CLOCK_SetClkDiv(kCLOCK_DivFlexcom1Clk, 1u);
 	CLOCK_AttachClk(kFRO12M_to_FLEXCOMM1);
@@ -215,6 +226,48 @@ static int frdm_mcxn947_init(void)
 	CLOCK_AttachClk(kFRO_HF_to_ADC0);
 #endif
 
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(usb1), okay) && CONFIG_USB_DC_NXP_EHCI
+	usb_phy_config_struct_t usbPhyConfig = {
+		BOARD_USB_PHY_D_CAL, BOARD_USB_PHY_TXCAL45DP, BOARD_USB_PHY_TXCAL45DM,
+	};
+
+	SPC0->ACTIVE_VDELAY = 0x0500;
+	/* Change the power DCDC to 1.8v (By default, DCDC is 1.8V), CORELDO to 1.1v (By default,
+	 * CORELDO is 1.0V)
+	 */
+	SPC0->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK;
+	SPC0->ACTIVE_CFG |= SPC_ACTIVE_CFG_DCDC_VDD_LVL(0x3) | SPC_ACTIVE_CFG_CORELDO_VDD_LVL(0x3) |
+			    SPC_ACTIVE_CFG_SYSLDO_VDD_DS_MASK | SPC_ACTIVE_CFG_DCDC_VDD_DS(0x2u);
+	/* Wait until it is done */
+	while (SPC0->SC & SPC_SC_BUSY_MASK) {
+	};
+	if (0u == (SCG0->LDOCSR & SCG_LDOCSR_LDOEN_MASK)) {
+		SCG0->TRIM_LOCK = 0x5a5a0001U;
+		SCG0->LDOCSR |= SCG_LDOCSR_LDOEN_MASK;
+		/* wait LDO ready */
+		while (0U == (SCG0->LDOCSR & SCG_LDOCSR_VOUT_OK_MASK)) {
+		};
+	}
+	SYSCON->AHBCLKCTRLSET[2] |= SYSCON_AHBCLKCTRL2_USB_HS_MASK |
+				    SYSCON_AHBCLKCTRL2_USB_HS_PHY_MASK;
+	SCG0->SOSCCFG &= ~(SCG_SOSCCFG_RANGE_MASK | SCG_SOSCCFG_EREFS_MASK);
+	/* xtal = 20 ~ 30MHz */
+	SCG0->SOSCCFG = (1U << SCG_SOSCCFG_RANGE_SHIFT) | (1U << SCG_SOSCCFG_EREFS_SHIFT);
+	SCG0->SOSCCSR |= SCG_SOSCCSR_SOSCEN_MASK;
+	while (1) {
+		if (SCG0->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK) {
+			break;
+		}
+	}
+	SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK |
+			      SYSCON_CLOCK_CTRL_CLKIN_ENA_FM_USBH_LPT_MASK;
+	CLOCK_EnableClock(kCLOCK_UsbHs);
+	CLOCK_EnableClock(kCLOCK_UsbHsPhy);
+	CLOCK_EnableUsbhsPhyPllClock(kCLOCK_Usbphy480M, BOARD_XTAL0_CLK_HZ);
+	CLOCK_EnableUsbhsClock();
+	USB_EhciPhyInit(kUSB_ControllerEhci0, BOARD_XTAL0_CLK_HZ, &usbPhyConfig);
+#endif
+
 	/* Set SystemCoreClock variable. */
 	SystemCoreClock = CLOCK_INIT_CORE_CLOCK;
 

boards/nxp/frdm_mcxn947/doc/index.rst

@@ -88,6 +88,8 @@ The FRDM-MCXN947 board configuration supports the following hardware features:
 +-----------+------------+-------------------------------------+
 | ADC       | on-chip    | adc                                 |
 +-----------+------------+-------------------------------------+
+| USBHS     | on-chip    | USB device                          |
++-----------+------------+-------------------------------------+
 
 Targets available
 ==================

boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dts

@@ -161,3 +161,7 @@
 &lpadc0 {
 	status = "okay";
 };
+
+zephyr_udc0: &usb1 {
+	status = "okay";
+};

boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml

@@ -26,4 +26,5 @@ supported:
   - sdhc
   - regulator
   - adc
+  - usb_device
 vendor: nxp