diff --git a/soc/arm/atmel_sam/sam4s/soc.c b/soc/arm/atmel_sam/sam4s/soc.c index e1041f8a2fc..5efaa35e894 100644 --- a/soc/arm/atmel_sam/sam4s/soc.c +++ b/soc/arm/atmel_sam/sam4s/soc.c @@ -3,6 +3,7 @@ * Copyright (c) 2016 Intel Corporation. * Copyright (c) 2017 Justin Watson * Copyright (c) 2023 Gerson Fernando Budke + * Copyright (c) 2023 Basalte bv * * SPDX-License-Identifier: Apache-2.0 */ @@ -15,9 +16,9 @@ * for the Atmel SAM4S series processor. */ -#include -#include #include +#include +#include /** * @brief Setup various clock on SoC at boot time. @@ -29,158 +30,36 @@ */ static ALWAYS_INLINE void clock_init(void) { - uint32_t reg_val; + /* Switch the main clock to the internal OSC with 12MHz */ + soc_pmc_switch_mainck_to_fastrc(SOC_PMC_FAST_RC_FREQ_12MHZ); -#ifdef CONFIG_SOC_ATMEL_SAM4S_EXT_SLCK - /* Switch slow clock to the external 32 KHz crystal oscillator. */ - SUPC->SUPC_CR = SUPC_CR_KEY_PASSWD | SUPC_CR_XTALSEL_CRYSTAL_SEL; + /* Switch MCK (Master Clock) to the main clock */ + soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_MAIN_CLK); - /* Wait for oscillator to be stabilized. */ - while (!(SUPC->SUPC_SR & SUPC_SR_OSCSEL)) { - ; - } - -#endif /* CONFIG_SOC_ATMEL_SAM4S_EXT_SLCK */ - -#ifdef CONFIG_SOC_ATMEL_SAM4S_EXT_MAINCK - /* - * Setup main external crystal oscillator. - */ - - /* Start the external crystal oscillator. */ - PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD - /* Fast RC oscillator frequency is at 4 MHz. */ - | CKGR_MOR_MOSCRCF_4_MHz - /* - * We select maximum setup time. While start up time - * could be shortened this optimization is not deemed - * critical right now. - */ - | CKGR_MOR_MOSCXTST(0xFFu) - /* RC oscillator must stay on. */ - | CKGR_MOR_MOSCRCEN - | CKGR_MOR_MOSCXTEN; - - /* Wait for oscillator to be stabilized. */ - while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)) { - ; - } - - /* Select the external crystal oscillator as the main clock source. */ - PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD - | CKGR_MOR_MOSCRCF_4_MHz - | CKGR_MOR_MOSCRCEN - | CKGR_MOR_MOSCXTEN - | CKGR_MOR_MOSCXTST(0xFFu) - | CKGR_MOR_MOSCSEL; - - /* Wait for external oscillator to be selected. */ - while (!(PMC->PMC_SR & PMC_SR_MOSCSELS)) { - ; - } - - /* Turn off RC oscillator, not used any longer, to save power */ - PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD - | CKGR_MOR_MOSCSEL - | CKGR_MOR_MOSCXTST(0xFFu) - | CKGR_MOR_MOSCXTEN; - - /* Wait for the RC oscillator to be turned off. */ - while (PMC->PMC_SR & PMC_SR_MOSCRCS) { - ; - } - -#ifdef CONFIG_SOC_ATMEL_SAM4S_WAIT_MODE - /* - * Instruct CPU to enter Wait mode instead of Sleep mode to - * keep Processor Clock (HCLK) and thus be able to debug - * CPU using JTAG. - */ - PMC->PMC_FSMR |= PMC_FSMR_LPM; + EFC0->EEFC_FMR = EEFC_FMR_FWS(0); +#if defined(ID_EFC1) + EFC1->EEFC_FMR = EEFC_FMR_FWS(0); #endif -#else - /* Setup main fast RC oscillator. */ - /* - * NOTE: MOSCRCF must be changed only if MOSCRCS is set in the PMC_SR - * register, should normally be the case. - */ - while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)) { - ; + soc_pmc_enable_clock_failure_detector(); + + if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM4S_EXT_SLCK)) { + soc_supc_slow_clock_select_crystal_osc(); } - /* Set main fast RC oscillator to 12 MHz. */ - PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD - | CKGR_MOR_MOSCRCF_12_MHz - | CKGR_MOR_MOSCRCEN; + if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM4S_EXT_MAINCK)) { + /* + * Setup main external crystal oscillator. + */ - /* Wait for RC oscillator to stabilize. */ - while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)) { - ; - } -#endif /* CONFIG_SOC_ATMEL_SAM4S_EXT_MAINCK */ - - /* - * Setup PLLA - */ - - /* Switch MCK (Master Clock) to the main clock first. */ - reg_val = PMC->PMC_MCKR & ~PMC_MCKR_CSS_Msk; - PMC->PMC_MCKR = reg_val | PMC_MCKR_CSS_MAIN_CLK; - - /* Wait for clock selection to complete. */ - while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) { - ; + /* We select maximum setup time. + * While start up time could be shortened + * this optimization is not deemed + * critical now. + */ + soc_pmc_switch_mainck_to_xtal(false, 0xff); } - /* Setup PLLA. */ - PMC->CKGR_PLLAR = CKGR_PLLAR_ONE - | CKGR_PLLAR_MULA(CONFIG_SOC_ATMEL_SAM4S_PLLA_MULA) - | CKGR_PLLAR_PLLACOUNT(0x3Fu) - | CKGR_PLLAR_DIVA(CONFIG_SOC_ATMEL_SAM4S_PLLA_DIVA); - - /* - * NOTE: Both MULA and DIVA must be set to a value greater than 0 or - * otherwise PLL will be disabled. In this case we would get stuck in - * the following loop. - */ - - /* Wait for PLL lock. */ - while (!(PMC->PMC_SR & PMC_SR_LOCKA)) { - ; - } - - /* - * Final setup of the Master Clock - */ - - /* - * NOTE: PMC_MCKR must not be programmed in a single write operation. - * If CSS or PRES are modified we must wait for MCKRDY bit to be - * set again. - */ - - /* Setup prescaler - PLLA Clock / Processor Clock (HCLK). */ - reg_val = PMC->PMC_MCKR & ~PMC_MCKR_PRES_Msk; - PMC->PMC_MCKR = reg_val | PMC_MCKR_PRES_CLK_1; - - /* Wait for Master Clock setup to complete */ - while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) { - ; - } - - /* Finally select PLL as Master Clock source. */ - reg_val = PMC->PMC_MCKR & ~PMC_MCKR_CSS_Msk; - PMC->PMC_MCKR = reg_val | PMC_MCKR_CSS_PLLA_CLK; - - /* Wait for Master Clock setup to complete. */ - while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) { - ; - } -} - -void z_arm_platform_init(void) -{ /* * Set FWS (Flash Wait State) value before increasing Master Clock * (MCK) frequency. Look at table 44.73 in the SAM4S datasheet. @@ -188,9 +67,44 @@ void z_arm_platform_init(void) * hurt lower clock frequencies. However, a high frequency with too * few read cycles could cause flash read problems. FWS 5 (6 cycles) * is the safe setting for all of this SoCs usable frequencies. - * TODO: Add code to handle SAM4SD devices that have 2 EFCs. */ EFC0->EEFC_FMR = EEFC_FMR_FWS(5); +#if defined(ID_EFC1) + EFC1->EEFC_FMR = EEFC_FMR_FWS(5); +#endif + + /* + * Setup PLLA + */ + soc_pmc_enable_pllack(CONFIG_SOC_ATMEL_SAM4S_PLLA_MULA, 0x3Fu, + CONFIG_SOC_ATMEL_SAM4S_PLLA_DIVA); + + /* + * Final setup of the Master Clock + */ + + /* prescaler has to be set before PLL lock */ + soc_pmc_mck_set_prescaler(1); + + /* Select PLL as Master Clock source. */ + soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_PLLA_CLK); + + /* Disable internal fast RC if we have an external crystal oscillator */ + if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM4S_EXT_MAINCK)) { + soc_pmc_osc_disable_fastrc(); + } +} + +void z_arm_platform_init(void) +{ + if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM4S_WAIT_MODE)) { + /* + * Instruct CPU to enter Wait mode instead of Sleep mode to + * keep Processor Clock (HCLK) and thus be able to debug + * CPU using JTAG. + */ + soc_pmc_enable_waitmode(); + } /* Setup system clocks. */ clock_init();