x86/cache: fix issues in arch dcache flush function
Correct the wrong operand of clflush instruction. The old operand points to a location inside stack and doesn't work. The new one works well by taking linux kernel code as reference. End address instead of size should get round up Add Kconfig option to disable the usage of mfence intruction for SoC that has clfulsh but no mfence supported. Signed-off-by: Dong Wang <dong.d.wang@intel.com>
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2 changed files with 17 additions and 5 deletions
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@ -170,4 +170,12 @@ config X86_USE_THREAD_LOCAL_STORAGE
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help
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Internal config to enable thread local storage.
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config X86_MFENCE_INSTRUCTION_SUPPORTED
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bool "X86 MFENCE instruction supported"
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default y
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depends on CACHE_MANAGEMENT
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help
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Set n to disable the use of MFENCE instruction in arch_dcache_flush()
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for X86 CPUs have CLFLUSH instruction but no MFENCE
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endif # !X86_64
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@ -33,20 +33,24 @@ static void arch_dcache_flush(void *start_addr, size_t size)
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{
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size_t line_size = sys_cache_data_line_size_get();
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uintptr_t start = (uintptr_t)start_addr;
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uintptr_t end;
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uintptr_t end = start + size;
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if (line_size == 0U) {
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return;
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}
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size = ROUND_UP(size, line_size);
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end = start + size;
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end = ROUND_UP(end, line_size);
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for (; start < end; start += line_size) {
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__asm__ volatile("clflush %0;\n\t" : : "m"(start));
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__asm__ volatile("clflush %0;\n\t" :
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"+m"(*(volatile char *)start));
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}
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__asm__ volatile("mfence;\n\t");
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#if defined(CONFIG_X86_MFENCE_INSTRUCTION_SUPPORTED)
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__asm__ volatile("mfence;\n\t":::"memory");
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#else
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__asm__ volatile("lock; addl $0,-4(%%esp);\n\t":::"memory", "cc");
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#endif
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}
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int arch_dcache_range(void *addr, size_t size, int op)
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