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driver: scfg: npcx: cleanup low-voltage detection configuration

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Cleanup npcx low-voltage (1.8V) detection configuration. It removes
unused soc utilities, macros, and DT node. We will configure this
feature by GPIO driver with GPIO_VOLTAGE_1P8 flag later.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This commit is contained in:
Mulin Chao 2022-07-18 02:13:40 -07:00 • committed by Carles Cufí
commit a5fee4c6de
7 changed files with 0 additions and 185 deletions
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10
drivers/gpio/gpio_npcx.c
View file

@ -98,7 +98,6 @@ void npcx_gpio_disable_io_pads(const struct device *dev, int pin)
static int gpio_npcx_config(const struct device *dev,
gpio_pin_t pin, gpio_flags_t flags)
{
const struct gpio_npcx_config *const config = dev->config;
struct gpio_reg *const inst = HAL_INSTANCE(dev);
uint32_t mask = BIT(pin);
@ -122,15 +121,6 @@ static int gpio_npcx_config(const struct device *dev,
inst->PDIR &= ~mask;
}
/*
* If this IO pad is configured for low-voltage power supply, the GPIO
* driver must set the related PORTx_OUT_TYPE bit to 1 (i.e. select io
* type to open-drain) also.
*/
if (npcx_lvol_is_enabled(config->port, pin)) {
flags |= GPIO_OPEN_DRAIN;
}
/* Select open drain 0:push-pull 1:open-drain */
if ((flags & GPIO_OPEN_DRAIN) != 0) {
inst->PTYPE |= mask;

10
dts/arm/nuvoton/npcx.dtsi
View file

@ -44,16 +44,6 @@
pinmux = <>;
};
def-lvol-io-list {
compatible = "nuvoton,npcx-lvolctrl-def";
/* Put low-voltage io pads into "lvol-io-pads" property if the
* detection level of them is 1.8V, For example, if the bus
* voltage of i2c1_0 port is 1.8V, this property should be:
* lvol-io-pads = <&lvol_io90 &lvol_io87>;
*/
lvol-io-pads = <>;
};
/** Dummy pinctrl node. It will be initialized with defaults based on the SoC series.
* Then, the user can override the pin control options at the board level.
*/

14
dts/bindings/pinctrl/nuvoton,npcx-lvolctrl-def.yaml
View file

@ -1,14 +0,0 @@
# Copyright (c) 2020 Nuvoton Technology Corporation.
# SPDX-License-Identifier: Apache-2.0
description: Nuvoton, NPCX Default Low-Voltage Configurations
compatible: "nuvoton,npcx-lvolctrl-def"
include: [base.yaml]
properties:
lvol-io-pads:
type: phandles
required: false
description: list of low-voltage configurations that need to set by default

10
soc/arm/nuvoton_npcx/common/power.c
View file

@ -99,11 +99,6 @@ static void npcx_power_enter_system_sleep(int slp_mode, int wk_mode)
npcx_clock_control_turn_on_system_sleep(slp_mode == NPCX_DEEP_SLEEP,
wk_mode == NPCX_INSTANT_WAKE_UP);
/* A bypass in npcx7 series to prevent leakage in low-voltage pads */
if (IS_ENABLED(CONFIG_SOC_SERIES_NPCX7)) {
npcx_lvol_suspend_io_pads();
}
/* Turn on eSPI/LPC host access wake-up interrupt. */
if (IS_ENABLED(CONFIG_ESPI_NPCX)) {
npcx_host_enable_access_interrupt();
@ -134,11 +129,6 @@ static void npcx_power_enter_system_sleep(int slp_mode, int wk_mode)
npcx_host_disable_access_interrupt();
}
/* A bypass in npcx7 series to prevent leakage in low-voltage pads */
if (IS_ENABLED(CONFIG_SOC_SERIES_NPCX7)) {
npcx_lvol_restore_io_pads();
}
/* Turn off system sleep mode. */
npcx_clock_control_turn_off_system_sleep();
}

47
soc/arm/nuvoton_npcx/common/scfg.c
View file

@ -43,8 +43,6 @@ static const struct npcx_alt def_alts[] = {
NPCX_NO_GPIO_ALT_ITEM)
};
static const struct npcx_lvol def_lvols[] = NPCX_DT_IO_LVOL_ITEMS_DEF_LIST;
static const struct npcx_scfg_config npcx_scfg_cfg = {
.base_scfg = DT_REG_ADDR_BY_NAME(DT_NODELABEL(scfg), scfg),
.base_glue = DT_REG_ADDR_BY_NAME(DT_NODELABEL(scfg), glue),
@ -76,48 +74,6 @@ static void npcx_pinctrl_alt_sel(const struct npcx_alt *alt, int alt_func)
}
/* Platform specific pin-control functions */
void npcx_lvol_pads_configure(void)
{
const uint32_t scfg_base = npcx_scfg_cfg.base_scfg;
for (int i = 0; i < ARRAY_SIZE(def_lvols); i++) {
NPCX_LV_GPIO_CTL(scfg_base, def_lvols[i].ctrl)
|= BIT(def_lvols[i].bit);
LOG_DBG("IO%x%x turn on low-voltage", def_lvols[i].io_port,
def_lvols[i].io_bit);
}
}
void npcx_lvol_restore_io_pads(void)
{
for (int i = 0; i < ARRAY_SIZE(def_lvols); i++) {
npcx_gpio_enable_io_pads(
npcx_get_gpio_dev(def_lvols[i].io_port),
def_lvols[i].io_bit);
}
}
void npcx_lvol_suspend_io_pads(void)
{
for (int i = 0; i < ARRAY_SIZE(def_lvols); i++) {
npcx_gpio_disable_io_pads(
npcx_get_gpio_dev(def_lvols[i].io_port),
def_lvols[i].io_bit);
}
}
bool npcx_lvol_is_enabled(int port, int pin)
{
for (int i = 0; i < ARRAY_SIZE(def_lvols); i++) {
if (def_lvols[i].io_port == port &&
def_lvols[i].io_bit == pin) {
return true;
}
}
return false;
}
void npcx_pinctrl_i2c_port_sel(int controller, int port)
{
struct glue_reg *const inst_glue = HAL_GLUE_INST();
@ -173,9 +129,6 @@ static int npcx_scfg_init(const struct device *dev)
npcx_pinctrl_alt_sel(&def_alts[i], 0);
}
/* Configure default low-voltage pads */
npcx_lvol_pads_configure();
return 0;
}

69
soc/arm/nuvoton_npcx/common/soc_dt.h
View file

@ -333,75 +333,6 @@
1), \
}
/**
* @brief Get a node from path '/def_lvol_io_list' which has a property
* 'lvol-io-pads' contains low-voltage configurations and need to set
* by default.
*
* @return node identifier with that path.
*/
#define NPCX_DT_NODE_DEF_LVOL_LIST DT_PATH(def_lvol_io_list)
/**
* @brief Length of npcx_lvol structures in 'lvol-io-pads' property
*
* @return length of 'lvol-io-pads' prop which type is 'phandles'
*/
#define NPCX_DT_LVOL_ITEMS_LEN DT_PROP_LEN(NPCX_DT_NODE_DEF_LVOL_LIST, \
lvol_io_pads)
/**
* @brief Get phandle from 'lvol-io-pads' prop which type is 'phandles' at index
* 'i'
*
* @param i index of 'lvol-io-pads' prop which type is 'phandles'
* @return phandle from 'lvol-io-pads' prop at index 'i'
*/
#define NPCX_DT_PHANDLE_FROM_LVOL_IO_PADS(i) \
DT_PHANDLE_BY_IDX(NPCX_DT_NODE_DEF_LVOL_LIST, lvol_io_pads, i)
/**
* @brief Construct a npcx_lvol structure from 'lvol-io-pads' property at index
* 'i'.
*
* @param i index of 'lvol-io-pads' prop which type is 'phandles'
* @return npcx_lvol item from 'lvol-io-pads' property at index 'i'
*/
#define NPCX_DT_LVOL_ITEMS_BY_IDX(i, _) \
{ \
.io_port = DT_PHA(NPCX_DT_PHANDLE_FROM_LVOL_IO_PADS(i), \
lvols, io_port), \
.io_bit = DT_PHA(NPCX_DT_PHANDLE_FROM_LVOL_IO_PADS(i), \
lvols, io_bit), \
.ctrl = DT_PHA(NPCX_DT_PHANDLE_FROM_LVOL_IO_PADS(i), \
lvols, ctrl), \
.bit = DT_PHA(NPCX_DT_PHANDLE_FROM_LVOL_IO_PADS(i), \
lvols, bit), \
}
/**
* @brief Macro function to construct a list of npcx_lvol items by UTIL_LISTIFY
* func.
*
* Example devicetree fragment:
* / {
* def_lvol_io_list {
* compatible = "nuvoton,npcx-lvolctrl-def";
* lvol-io-pads = <&lvol_io90 // I2C1_SCL0 1.8V support
* &lvol_io87>; // I2C1_SDA0 1,8V support
* };
* };
*
* Example usage:
* static const struct npcx_lvol def_lvols[] = NPCX_DT_IO_LVOL_ITEMS_DEF_LIST;
*
* @return an array of npcx_lvol items which configure low-voltage support
*/
#define NPCX_DT_IO_LVOL_ITEMS_DEF_LIST { \
LISTIFY(NPCX_DT_LVOL_ITEMS_LEN, \
NPCX_DT_LVOL_ITEMS_BY_IDX, (,), _) \
}
/**
* @brief Check if the host interface type is automatically configured by
* booter.

25
soc/arm/nuvoton_npcx/common/soc_pins.h
View file

@ -62,31 +62,6 @@ int npcx_pinctrl_flash_write_protect_set(void);
*/
bool npcx_pinctrl_flash_write_protect_is_set(void);
/**
* @brief Restore all connections between IO pads that support low-voltage power
* supply and GPIO hardware devices. This utility is used for solving a
* leakage current issue found in npcx7 series. The npcx9 and later
* series fixed the issue and needn't it.
*/
void npcx_lvol_restore_io_pads(void);
/**
* @brief Disable all connections between IO pads that support low-voltage power
* supply and GPIO hardware devices. This utility is used for solving a
* leakage current issue found in npcx7 series. The npcx9 and later
* series fixed the issue and needn't it.
*/
void npcx_lvol_suspend_io_pads(void);
/**
* @brief Get the low-voltage power supply status of GPIO pads
*
* @param port port index of GPIO device
* @param pin pin of GPIO device
* @return 1 means the low-voltage power supply is enabled, otherwise disabled.
*/
bool npcx_lvol_is_enabled(int port, int pin);
/**
* @brief Select the host interface type
*