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soc: renesas: ra8d1: Enable I cache and D cache

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Enabling I cache and D cache in RA8D1 init hook to improve
code execution performance

Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
This commit is contained in:
Duy Nguyen 2025-02-05 10:30:42 +07:00 • committed by Benjamin Cabé
commit a5e035bc96
2 changed files with 27 additions and 0 deletions
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3
soc/renesas/ra/ra8d1/Kconfig.defconfig
View file

@ -10,4 +10,7 @@ config NUM_IRQS
config FLASH_FILL_BUFFER_SIZE
default 128
config CACHE_MANAGEMENT
default y
endif # SOC_SERIES_RA8D1

24
soc/renesas/ra/ra8d1/soc.c
View file

@ -17,10 +17,14 @@
#include <zephyr/arch/arm/nmi.h>
#include <zephyr/irq.h>
#include <zephyr/logging/log.h>
#include <zephyr/sys/barrier.h>
#include <zephyr/cache.h>
LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
#include <bsp_api.h>
#define CCR_CACHE_ENABLE (SCB_CCR_IC_Msk | SCB_CCR_BP_Msk | SCB_CCR_LOB_Msk)
uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT;
volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT;
@ -34,4 +38,24 @@ void soc_early_init_hook(void)
{
SystemCoreClock = BSP_MOCO_HZ;
g_protect_pfswe_counter = 0;
SCB->CCR = (uint32_t)CCR_CACHE_ENABLE;
barrier_dsync_fence_full();
barrier_isync_fence_full();
/* Apply Arm Cortex-M85 errata workarounds for D-Cache
* Attributing all cacheable memory as write-through set FORCEWT bit in MSCR register.
* Set bit 16 in ACTLR to 1.
* See erratum 3175626 and 3190818 in the Cortex-M85 AT640 and Cortex-M85 with FPU AT641
* Software Developer Errata Notice (Date of issue: March 07, 2024, Document version: 13.0,
* Document ID: SDEN-2236668).
*/
MEMSYSCTL->MSCR |= MEMSYSCTL_MSCR_FORCEWT_Msk;
barrier_dsync_fence_full();
barrier_isync_fence_full();
ICB->ACTLR |= (1U << 16U);
barrier_dsync_fence_full();
barrier_isync_fence_full();
sys_cache_data_enable();
}