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dts: arm: nxp: add initial LPC55S16 devicetree

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Add initial devicetree for the NXP LPC55S16. Only non-secure (ns)
access is supported for now.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
This commit is contained in:
Henrik Brix Andersen 2020-04-18 20:13:48 +02:00 • committed by Maureen Helm
commit a5d7946a73
2 changed files with 202 additions and 0 deletions
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dts/arm/nxp/nxp_lpc55S16_ns.dtsi Normal file
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/*
* Copyright (c) 2020 Henrik Brix Andersen <henrik@brixandersen.dk>
*
* SPDX-License-Identifier: Apache-2.0
*/
/ {
soc {
sram: sram@400000 {
ranges = <0x4000000 0x4000000 0x20000000>;
};
peripheral: peripheral@40000000 {
ranges = <0x0 0x40000000 0x10000000>;
};
};
};
#include "nxp_lpc55S1x_common.dtsi"

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dts/arm/nxp/nxp_lpc55S1x_common.dtsi Normal file
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/*
* Copyright (c) 2020 Henrik Brix Andersen <henrik@brixandersen.dk>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <arm/armv8-m.dtsi>
#include <dt-bindings/gpio/gpio.h>
#include <mem.h>
/ {
aliases {
gpio-0 = &gpio0;
gpio-1 = &gpio1;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "arm,cortex-m33f";
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
mpu: mpu@e000ed90 {
compatible = "arm,armv8m-mpu";
reg = <0xe000ed90 0x40>;
arm,num-mpu-regions = <8>;
};
};
};
};
&sram {
#address-cells = <1>;
#size-cells = <1>;
sramx: memory@4000000 {
compatible = "mmio-sram";
reg = <0x4000000 DT_SIZE_K(16)>;
};
sram0: memory@20000000 {
compatible = "mmio-sram";
reg = <0x20000000 DT_SIZE_K(32)>;
};
sram1: memory@20008000 {
compatible = "mmio-sram";
reg = <0x20008000 DT_SIZE_K(16)>;
};
sram2: memory@2000c000 {
compatible = "mmio-sram";
reg = <0x2000c000 DT_SIZE_K(16)>;
};
sram4: memory@20010000 {
/* Conencted to USB bus*/
compatible = "mmio-sram";
reg = <0x20010000 DT_SIZE_K(16)>;
};
};
&peripheral {
#address-cells = <1>;
#size-cells = <1>;
iap: flash-controller@34000 {
compatible = "nxp,lpc-iap";
label = "FLASH_IAP";
reg = <0x34000 0x18>;
#address-cells = <1>;
#size-cells = <1>;
flash0: flash@0 {
compatible = "soc-nv-flash";
label = "MCUX_FLASH";
reg = <0x0 DT_SIZE_K(246)>;
erase-block-size = <512>;
write-block-size = <512>;
};
flash_reserved: flash@3d800 {
compatible = "soc-nv-flash";
reg = <0x0003d800 DT_SIZE_K(10)>;
status = "disabled";
};
boot_rom: flash@3000000 {
compatible = "soc-nv-flash";
reg = <0x3000000 DT_SIZE_K(128)>;
};
};
gpio0: gpio@0 {
compatible = "nxp,lpc-gpio";
reg = <0x8c000 0x2488>;
interrupts = <2 2>;
label = "GPIO_0";
gpio-controller;
#gpio-cells = <2>;
};
gpio1: gpio@1 {
compatible = "nxp,lpc-gpio";
reg = <0x8c000 0x2488>;
interrupts = <3 2>;
label = "GPIO_1";
gpio-controller;
#gpio-cells = <2>;
};
flexcomm0: flexcomm@86000 {
compatible = "nxp,lpc-flexcomm";
reg = <0x86000 0x1000>;
interrupts = <14 0>;
label = "FLEXCOMM_0";
status = "disabled";
};
flexcomm1: flexcomm@87000 {
compatible = "nxp,lpc-flexcomm";
reg = <0x87000 0x1000>;
interrupts = <15 0>;
label = "FLEXCOMM_1";
status = "disabled";
};
flexcomm2: flexcomm@88000 {
compatible = "nxp,lpc-flexcomm";
reg = <0x88000 0x1000>;
interrupts = <16 0>;
label = "FLEXCOMM_2";
status = "disabled";
};
flexcomm3: flexcomm@89000 {
compatible = "nxp,lpc-flexcomm";
reg = <0x89000 0x1000>;
interrupts = <17 0>;
label = "FLEXCOMM_3";
status = "disabled";
};
flexcomm4: flexcomm@8a000 {
compatible = "nxp,lpc-flexcomm";
reg = <0x8a000 0x1000>;
interrupts = <18 0>;
label = "FLEXCOMM_4";
status = "disabled";
};
flexcomm5: flexcomm@96000 {
compatible = "nxp,lpc-flexcomm";
reg = <0x96000 0x1000>;
interrupts = <19 0>;
label = "FLEXCOMM_5";
status = "disabled";
};
flexcomm6: flexcomm@97000 {
compatible = "nxp,lpc-flexcomm";
reg = <0x97000 0x1000>;
interrupts = <20 0>;
label = "FLEXCOMM_6";
status = "disabled";
};
flexcomm7: flexcomm@98000 {
compatible = "nxp,lpc-flexcomm";
reg = <0x98000 0x1000>;
interrupts = <21 0>;
label = "FLEXCOMM_7";
status = "disabled";
};
};
&nvic {
arm,num-irq-priority-bits = <3>;
};