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dts: bindings: add title property

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This adds a proper, concise, title property to a bunch of bindings for
which the first sentence of their description (which used to be a
makeshift title) was really long

Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
This commit is contained in:
Benjamin Cabé 2025-05-14 21:13:52 +02:00 • committed by Benjamin Cabé
commit a58e65908c
28 changed files with 105 additions and 59 deletions
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2
dts/bindings/clock/gd,gd32-cctl.yaml
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# Copyright (c) 2022, Teslabs Engineering S.L. # Copyright (c) 2022, Teslabs Engineering S.L.
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
title: Gigadevice RCU (Reset and Clock Unit) - Clock Controller
description: | description: |
Gigadevice Reset and Clock Unit (RCU) if a multi-function peripheral in Gigadevice Reset and Clock Unit (RCU) if a multi-function peripheral in
charge of reset control (RCTL) and clock control (CCTL) for all SoC charge of reset control (RCTL) and clock control (CCTL) for all SoC

5
dts/bindings/ethernet/st,stm32-ethernet-controller.yaml
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# Copyright The Zephyr Project Contributors # Copyright The Zephyr Project Contributors
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
title: STM32 Ethernet Controller
description: | description: |
ST STM32 Ethernet controller, contains the Ethernet MAC Contains the Ethernet MAC and the MDIO as child nodes.
and the MDIO as a child nodes.
compatible: "st,stm32-ethernet-controller" compatible: "st,stm32-ethernet-controller"

3
dts/bindings/memory-controllers/nxp,flexram.yaml
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# Copyright 2023 NXP # Copyright 2023 NXP
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
title: NXP FlexRAM on-chip RAM controller
description: | description: |
NXP FlexRAM on-chip ram controller
If the flexram,bank-spec property is specified, then the flexram will be If the flexram,bank-spec property is specified, then the flexram will be
dynamically reconfigured to the configuration specified at runtime. An dynamically reconfigured to the configuration specified at runtime. An
example to configure the flexram dynamically using the example to configure the flexram dynamically using the

2
dts/bindings/mfd/gd,gd32-rcu.yaml
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# Copyright (c) 2022, Teslabs Engineering S.L. # Copyright (c) 2022, Teslabs Engineering S.L.
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
title: Gigadevice RCU (Reset and Clock Unit)
description: | description: |
Gigadevice Reset and Clock Unit (RCU) if a multi-function peripheral in Gigadevice Reset and Clock Unit (RCU) if a multi-function peripheral in
charge of reset control (RCTL) and clock control (CCTL) for all SoC charge of reset control (RCTL) and clock control (CCTL) for all SoC

8
dts/bindings/pinctrl/ambiq,apollo3-pinctrl.yaml
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# Copyright (c) 2023 Ambiq Micro Inc. <www.ambiq.com> # Copyright (c) 2023 Ambiq Micro Inc. <www.ambiq.com>
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
title: Ambiq Apollo3 Pin Controller
description: | description: |
The Ambiq Apollo3 pin controller is a node responsible for controlling Singleton node responsible for controlling pin function selection and pin
pin function selection and pin properties, such as routing a UART0 TX properties, such as routing a UART0 TX to pin 60 and enabling the pullup
to pin 60 and enabling the pullup resistor on that pin. resistor on that pin.
The node has the 'pinctrl' node label set in your SoC's devicetree, The node has the 'pinctrl' node label set in your SoC's devicetree,
so you can modify it like this: so you can modify it like this:

8
dts/bindings/pinctrl/ambiq,apollo4-pinctrl.yaml
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@ -1,10 +1,12 @@
# Copyright (c) 2023 Antmicro <www.antmicro.com> # Copyright (c) 2023 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
title: Ambiq Apollo4 Pin Controller
description: | description: |
The Ambiq Apollo4 pin controller is a node responsible for controlling Singleton node responsible for controlling pin function selection and pin
pin function selection and pin properties, such as routing a UART0 TX properties, such as routing a UART0 TX to pin 60 and enabling the pullup
to pin 60 and enabling the pullup resistor on that pin. resistor on that pin.
The node has the 'pinctrl' node label set in your SoC's devicetree, The node has the 'pinctrl' node label set in your SoC's devicetree,
so you can modify it like this: so you can modify it like this:

8
dts/bindings/pinctrl/ambiq,apollo5-pinctrl.yaml
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@ -1,10 +1,12 @@
# Copyright (c) 2025 Ambiq Micro Inc. # Copyright (c) 2025 Ambiq Micro Inc.
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
title: Ambiq Apollo5 Pin Controller
description: | description: |
The Ambiq Apollo5 pin controller is a node responsible for controlling Singleton node responsible for controlling pin function selection and pin
pin function selection and pin properties, such as routing a UART0 TX properties, such as routing a UART0 TX to pin 60 and enabling the pullup
to pin 60 and enabling the pullup resistor on that pin. resistor on that pin.
The node has the 'pinctrl' node label set in your SoC's devicetree, The node has the 'pinctrl' node label set in your SoC's devicetree,
so you can modify it like this: so you can modify it like this:

7
dts/bindings/pinctrl/arm,mps2-pinctrl.yaml
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# Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com> # Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
title: Arm MPS2 Pin Controller
description: | description: |
The Arm Mps2 pin controller is a node responsible for controlling Node responsible for controlling pin function selection and pin properties,
pin function selection and pin properties, such as routing a UART3 TX such as routing a UART3 TX to pin 1.
to pin 1.
The node has the 'pinctrl' node label set in your SoC's devicetree, The node has the 'pinctrl' node label set in your SoC's devicetree,
so you can modify it like this: so you can modify it like this:

7
dts/bindings/pinctrl/arm,mps3-pinctrl.yaml
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# Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com> # Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
title: Arm MPS3 Pin Controller
description: | description: |
The Arm Mps3 pin controller is a node responsible for controlling Node responsible for controlling pin function selection and pin properties,
pin function selection and pin properties, such as routing a UART3 TX such as routing a UART3 TX to pin 1.
to pin 1.
The node has the 'pinctrl' node label set in your SoC's devicetree, The node has the 'pinctrl' node label set in your SoC's devicetree,
so you can modify it like this: so you can modify it like this:

2
dts/bindings/pinctrl/gd,gd32-afio.yaml
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@ -1,6 +1,8 @@
# Copyright (c) 2021 Teslabs Engineering S.L. # Copyright (c) 2021 Teslabs Engineering S.L.
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
title: GD32 AFIO (Alternate Function Input/Output)
description: | description: |
The AFIO peripheral is used to configure pin remapping, EXTI sources and, The AFIO peripheral is used to configure pin remapping, EXTI sources and,
when available, enable the I/O compensation cell. when available, enable the I/O compensation cell.

9
dts/bindings/pinctrl/gd,gd32-pinctrl-af.yaml
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# Copyright (c) 2021 Teslabs Engineering S.L. # Copyright (c) 2021 Teslabs Engineering S.L.
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
title: GD32 Pin Controller (AF Model)
description: | description: |
The GD32 pin controller (AF model) is a singleton node responsible for Singleton node responsible for controlling pin function selection and pin
controlling pin function selection and pin properties. For example, you can properties. For example, you can use this node to route USART0 RX to pin
use this node to route USART0 RX to pin PA10 and enable the pull-up resistor PA10 and enable the pull-up resistor on the pin.
on the pin.
The node has the 'pinctrl' node label set in your SoC's devicetree, The node has the 'pinctrl' node label set in your SoC's devicetree,
so you can modify it like this: so you can modify it like this:

9
dts/bindings/pinctrl/gd,gd32-pinctrl-afio.yaml
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@ -1,11 +1,12 @@
# Copyright (c) 2021 Teslabs Engineering S.L. # Copyright (c) 2021 Teslabs Engineering S.L.
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
title: GD32 Pin Controller (AFIO Model)
description: | description: |
The GD32 pin controller (AFIO model) is a singleton node responsible for Singleton node responsible for controlling pin function selection and pin
controlling pin function selection and pin properties. For example, you can properties. For example, you can use this node to route USART0 RX to pin
use this node to route USART0 RX to pin PA10 and enable the pull-up resistor PA10 and enable the pull-up resistor on the pin. Remapping is also supported.
on the pin. Remapping is also supported.
The node has the 'pinctrl' node label set in your SoC's devicetree, The node has the 'pinctrl' node label set in your SoC's devicetree,
so you can modify it like this: so you can modify it like this:

4
dts/bindings/pinctrl/infineon,xmc4xxx-pinctrl.yaml
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# Copyright (c) 2022, Andriy Gelman <andriy.gelman@gmail.com> # Copyright (c) 2022, Andriy Gelman <andriy.gelman@gmail.com>
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
title: Infineon XMC4XXX Pin Controller
description: | description: |
The Infineon XMC4XXX pin controller is responsible for connecting peripheral outputs Singleton node responsible for connecting peripheral outputs to specific port/pins
to specific port/pins (also known as alternate functions) and configures pin properties. to specific port/pins (also known as alternate functions) and configures pin properties.
The pinctrl settings are referenced in a device tree peripheral node. For example in a UART The pinctrl settings are referenced in a device tree peripheral node. For example in a UART

9
dts/bindings/pinctrl/nordic,nrf-pinctrl.yaml
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@ -1,11 +1,12 @@
# Copyright (c) 2021 Nordic Semiconductor ASA # Copyright (c) 2021 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
title: Nordic nRF family Pin Controller
description: | description: |
The nRF pin controller is a singleton node responsible for controlling Singleton node responsible for controlling pin function selection and pin
pin function selection and pin properties. For example, you can use this properties. For example, you can use this node to route UART0 RX to pin P0.1
node to route UART0 RX to pin P0.1 and enable the pull-up resistor on the and enable the pull-up resistor on the pin.
pin.
The node has the 'pinctrl' node label set in your SoC's devicetree, The node has the 'pinctrl' node label set in your SoC's devicetree,
so you can modify it like this: so you can modify it like this:

8
dts/bindings/pinctrl/raspberrypi,pico-pinctrl.yaml
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@ -2,10 +2,12 @@
# Copyright (c) 2021 Yonatan Schachter # Copyright (c) 2021 Yonatan Schachter
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
title: Raspberry Pi Pico Pin Controller
description: | description: |
The RPi Pico pin controller is a node responsible for controlling Singleton node responsible for controlling pin function selection and pin
pin function selection and pin properties, such as routing a UART0 Rx properties, such as routing a UART0 Rx to pin 1 and enabling the pullup
to pin 1 and enabling the pullup resistor on that pin. resistor on that pin.
The node has the 'pinctrl' node label set in your SoC's devicetree, The node has the 'pinctrl' node label set in your SoC's devicetree,
so you can modify it like this: so you can modify it like this:

7
dts/bindings/pinctrl/renesas,ra-pincrl-pfs.yaml
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@ -1,10 +1,11 @@
# Copyright (c) 2024 Renesas Electronics Corporation # Copyright (c) 2024 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
title: Renesas RA Pin Controller
description: | description: |
The Renesas RA pin controller is a node responsible for controlling Node responsible for controlling pin function selection and pin properties,
pin function selection and pin properties, such as routing a SCI0 RXD such as routing a SCI0 RXD to P610.
to P610.
The node has the 'pinctrl' node label set in your SoC's devicetree, The node has the 'pinctrl' node label set in your SoC's devicetree,
so you can modify it like this: so you can modify it like this:

7
dts/bindings/pinctrl/renesas,rzn-pinctrl.yaml
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# Copyright (c) 2025 Renesas Electronics Corporation # Copyright (c) 2025 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
title: Renesas RZ/N2L Pin Controller
description: | description: |
The Renesas RZ/N2L pin controller is a node responsible for controlling Singleton node responsible for controlling pin function selection and pin
pin function selection and pin properties, such as routing the TX and RX of UART0 properties, such as routing the TX and RX of UART0 to pin 5 and pin 6 of
to pin 5 and pin 6 of port 16. port 16.
The node has the 'pinctrl' node label set in your SoC's devicetree, The node has the 'pinctrl' node label set in your SoC's devicetree,
so you can modify it like this: so you can modify it like this:

8
dts/bindings/pinctrl/renesas,rzt2m-pinctrl.yaml
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@ -1,10 +1,12 @@
# Copyright (c) 2023 Antmicro <www.antmicro.com> # Copyright (c) 2023 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
title: Renesas RZ/T2M Pin Controller
description: | description: |
The Renesas RZ/T2M pin controller is a node responsible for controlling Singleton node responsible for controlling pin function selection and pin
pin function selection and pin properties, such as routing the TX and RX of UART0 properties, such as routing the TX and RX of UART0 to pin 5 and pin 6 of
to pin 5 and pin 6 of port 16. port 16.
The node has the 'pinctrl' node label set in your SoC's devicetree, The node has the 'pinctrl' node label set in your SoC's devicetree,
so you can modify it like this: so you can modify it like this:

8
dts/bindings/pinctrl/renesas,smartbond-pinctrl.yaml
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# Copyright (c) 2022 Renesas Electronics Corporation # Copyright (c) 2022 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
title: Renesas SmartBond Pin Controller
description: | description: |
The SmartBond pin controller is a singleton node responsible for controlling Singleton node responsible for controlling pin function selection and pin
pin function selection and pin properties, such as routing a UART RX to pin properties, such as routing a UART RX to pin P1.8 and enabling the pullup
P1.8 and enabling the pullup resistor on that pin. resistor on that pin.
The node has the 'pinctrl' node label set in your SoC's devicetree, The node has the 'pinctrl' node label set in your SoC's devicetree,
so you can modify it like this: so you can modify it like this:

6
dts/bindings/pinctrl/sensry,sy1xx-pinctrl.yaml
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# Copyright (c) 2024 sensry.io # Copyright (c) 2024 sensry.io
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
title: Sensry SY1xx Pin Controller
description: | description: |
The sensry SY1xx pin controller is a single node responsible for controlling Singleton node responsible for controlling pin configuration, such as pull-up,
pin configuration, such as pull-up, pull-down, tri-state, ... pull-down, tri-state, ...
The node has the 'pinctrl0' node label set in your SoC's devicetree, The node has the 'pinctrl0' node label set in your SoC's devicetree,
so you can modify it like this: so you can modify it like this:

7
dts/bindings/pinctrl/silabs,gecko-pinctrl.yaml
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# Copyright (c) 2022 Silicon Labs # Copyright (c) 2022 Silicon Labs
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
title: Silabs Gecko Pin Controller
description: | description: |
The Silabs pin controller is a singleton node responsible for controlling Singleton node responsible for controlling pin function selection and pin
pin function selection and pin properties. For example, you can use this properties. For example, you can use this node to route UART0 RX to pin P0.1
and enable the pull-up resistor on the pin.
node to route UART0 RX to pin P0.1 and enable the pull-up resistor on the node to route UART0 RX to pin P0.1 and enable the pull-up resistor on the
pin. pin.

5
dts/bindings/pinctrl/silabs,siwx91x-pinctrl.yaml
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@ -2,9 +2,10 @@
# Copyright (c) 2024 Silicon Laboratories Inc. # Copyright (c) 2024 Silicon Laboratories Inc.
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
title: Silabs SiWx91x Pin Controller
description: | description: |
The Silabs SiWx91x pin controller is a devicetree node tasked with selecting Node tasked with selecting the proper IO function for a given pin.
the proper IO function for a given pin.
The pinctrl settings are referenced in a device tree peripheral node. For The pinctrl settings are referenced in a device tree peripheral node. For
example when configuring a UART: example when configuring a UART:

9
dts/bindings/pinctrl/ti,cc32xx-pinctrl.yaml
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# Copyright (c) 2023 Nordic Semiconductor ASA # Copyright (c) 2023 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
title: TI CC32XX Pin Controller
description: | description: |
The TI CC32XX pin controller is a singleton node responsible for controlling Singleton node responsible for controlling pin function selection and pin
pin function selection and pin properties. For example, you can properties. For example, you can use this node to route UART0 RX to pin 55
use this node to route UART0 RX to pin 55 and enable the pull-up resistor and enable the pull-up resistor on the pin.
on the pin.
The node has the 'pinctrl' node label set in your SoC's devicetree, The node has the 'pinctrl' node label set in your SoC's devicetree,
so you can modify it like this: so you can modify it like this:

2
dts/bindings/reset/gd,gd32-rctl.yaml
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@ -1,6 +1,8 @@
# Copyright (c) 2022, Teslabs Engineering S.L. # Copyright (c) 2022, Teslabs Engineering S.L.
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
title: Gigadevice RCU (Reset and Clock Unit) - Reset Controller
description: | description: |
Gigadevice Reset and Clock Unit (RCU) if a multi-function peripheral in Gigadevice Reset and Clock Unit (RCU) if a multi-function peripheral in
charge of reset control (RCTL) and clock control (CCTL) for all SoC charge of reset control (RCTL) and clock control (CCTL) for all SoC

2
dts/bindings/sensor/bosch,bme680-i2c.yaml
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# Copyright (c) 2018, Bosch Sensortec GmbH # Copyright (c) 2018, Bosch Sensortec GmbH
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
title: Bosch BME680 Environmental Sensor (I2C)
description: | description: |
The BME680 is an integrated environmental sensor that measures The BME680 is an integrated environmental sensor that measures
temperature, pressure, humidity and air quality temperature, pressure, humidity and air quality

2
dts/bindings/sensor/bosch,bme680-spi.yaml
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@ -1,6 +1,8 @@
# Copyright (c) 2022, Leonard Pollak # Copyright (c) 2022, Leonard Pollak
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
title: Bosch BME680 Environmental Sensor (SPI)
description: | description: |
The BME680 is an integrated environmental sensor that measures The BME680 is an integrated environmental sensor that measures
temperature, pressure, humidity and air quality temperature, pressure, humidity and air quality

4
dts/bindings/sensor/nxp,s32-qdec.yaml
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# Copyright 2023 NXP # Copyright 2023 NXP
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
title: NXP S32 Quadrature Decoder
description: | description: |
Quadrature Decoder driver which processes encoder signals to determine motor revs Quadrature Decoder processes encoder signals to determine motor revs
with the cooperation of S32 IP blocks- eMIOS, TRGMUX and LCU. with the cooperation of S32 IP blocks- eMIOS, TRGMUX and LCU.
The sensor qdec application can be used for testing this driver. The sensor qdec application can be used for testing this driver.
The following example uses TRGMUX IN2 and IN3 to connect to LCU1 LC0 I0 and I1. The following example uses TRGMUX IN2 and IN3 to connect to LCU1 LC0 I0 and I1.

6
dts/bindings/usb/nxp,usbphy.yaml
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# Copyright 2024 NXP # Copyright 2024 NXP
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
title: NXP USB (Universal Serial Bus) High Speed PHY
description: | description: |
NXP USB high speed phy that is used on NXP RTxxxx, RTxxx, MCX, LPC and Kinetis NXP USB high speed PHY that is used on NXP RTxxxx, RTxxx, MCX, LPC and Kinetis
platforms if high speed usb is supported on these platforms. platforms if high speed usb is supported on these platforms.
Note: Only some LPC plafforms use it (like: LPC55S69, LPC55S28 and LPC55S16 etc). Note: Only some LPC platforms use it (like: LPC55S69, LPC55S28 and LPC55S16 etc).
compatible: "nxp,usbphy" compatible: "nxp,usbphy"