riscv: exception code mega simplification and optimization
Complete revamp of the exception entry code, including syscall handling.
Proper syscall frame exception trigger. Many correctness fixes, hacks
removal, etc. etc.
I tried to make this into several commits, but this stuff is all
inter-related and a pain to split.
The diffstat summary:
14 files changed, 250 insertions(+), 802 deletions(-)
Binary size (before):
text data bss dec hex filename
1104 0 0 1104 450 isr.S.obj
64 0 0 64 40 userspace.S.obj
Binary size (after):
text data bss dec hex filename
600 0 0 600 258 isr.S.obj
36 0 0 36 24 userspace.S.obj
Run of samples/userspace/syscall_perf (before):
*** Booting Zephyr OS build zephyr-v3.0.0-325-g3748accae018 ***
Main Thread started; qemu_riscv32
Supervisor thread started
User thread started
Supervisor thread(0x80010048): 384 cycles 509 instructions
User thread(0x80010140): 77312 cycles 77437 instructions
Run of samples/userspace/syscall_perf (after):
*** Booting Zephyr OS build zephyr-v3.0.0-326-g4c877a2753b3 ***
Main Thread started; qemu_riscv32
Supervisor thread started
User thread started
Supervisor thread(0x80010048): 384 cycles 509 instructions
User thread(0x80010138): 7040 cycles 7165 instructions
Yes, that's more than a 10x speed-up!
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
This commit is contained in:
Nicolas Pitre
Anas Nashif
parent
bfb7919ed0
commit
a50c433012
14 changed files with 258 additions and 810 deletions
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@ -12,20 +12,13 @@
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#include <core_pmp.h>
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#ifdef CONFIG_USERSPACE
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/*
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* Glogal variable used to know the current mode running.
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* Is not boolean because it must match the PMP granularity of the arch.
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*/
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uint32_t is_user_mode;
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bool irq_flag;
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#endif
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void z_thread_entry_wrapper(k_thread_entry_t thread,
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void *arg1,
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void *arg2,
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void *arg3);
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void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack,
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char *stack_ptr, k_thread_entry_t entry,
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void *p1, void *p2, void *p3)
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@ -64,13 +57,13 @@ void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack,
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* within the RISCV architecture implementation, initially set:
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* 1) MSTATUS to MSTATUS_DEF_RESTORE in the thread stack to enable
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* interrupts when the newly created thread will be scheduled;
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* 2) MEPC to the address of the z_thread_entry_wrapper in the thread
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* 2) MEPC to the address of the z_thread_entry in the thread
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* stack.
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* Hence, when going out of an interrupt/exception/context-switch,
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* after scheduling the newly created thread:
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* 1) interrupts will be enabled, as the MSTATUS register will be
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* restored following the MSTATUS value set within the thread stack;
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* 2) the core will jump to z_thread_entry_wrapper, as the program
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* 2) the core will jump to z_thread_entry, as the program
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* counter will be restored following the MEPC value set within the
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* thread stack.
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*/
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@ -81,7 +74,6 @@ void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack,
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if ((thread->base.user_options & K_FP_REGS) != 0) {
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stack_init->mstatus |= MSTATUS_FS_INIT;
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}
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stack_init->fp_state = 0;
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thread->callee_saved.fcsr = 0;
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#elif defined(CONFIG_FPU)
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/* Unshared FP mode: enable FPU of each thread. */
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@ -96,7 +88,9 @@ void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack,
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#if defined(CONFIG_USERSPACE)
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/* Clear user thread context */
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thread->arch.priv_stack_start = 0;
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thread->arch.user_sp = 0;
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/* the unwound stack pointer upon exiting exception */
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stack_init->sp = (ulong_t)(stack_init + 1);
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#endif /* CONFIG_USERSPACE */
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/* Assign thread entry point and mstatus.MPRV mode. */
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@ -107,7 +101,7 @@ void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack,
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} else {
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/* Supervisor thread */
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stack_init->mepc = (ulong_t)z_thread_entry_wrapper;
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stack_init->mepc = (ulong_t)z_thread_entry;
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#if defined(CONFIG_PMP_STACK_GUARD)
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/* Enable PMP in mstatus.MPRV mode for RISC-V machine mode
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@ -197,20 +191,6 @@ int arch_float_enable(struct k_thread *thread, unsigned int options)
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#ifdef CONFIG_USERSPACE
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/* Function used by Zephyr to switch a supervisor thread to a user thread */
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FUNC_NORETURN void arch_user_mode_enter(k_thread_entry_t user_entry,
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void *p1, void *p2, void *p3)
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{
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arch_syscall_invoke5((uintptr_t) arch_user_mode_enter,
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(uintptr_t) user_entry,
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(uintptr_t) p1,
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(uintptr_t) p2,
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(uintptr_t) p3,
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FORCE_SYSCALL_ID);
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CODE_UNREACHABLE;
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}
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/*
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* User space entry function
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*
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@ -218,34 +198,43 @@ FUNC_NORETURN void arch_user_mode_enter(k_thread_entry_t user_entry,
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* The conversion is one way, and threads which transition to user mode do
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* not transition back later, unless they are doing system calls.
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*/
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FUNC_NORETURN void z_riscv_user_mode_enter_syscall(k_thread_entry_t user_entry,
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void *p1, void *p2, void *p3)
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FUNC_NORETURN void arch_user_mode_enter(k_thread_entry_t user_entry,
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void *p1, void *p2, void *p3)
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{
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ulong_t top_of_user_stack = 0U;
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uintptr_t status;
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ulong_t top_of_user_stack, top_of_priv_stack;
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ulong_t status;
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/* Set up privileged stack */
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#ifdef CONFIG_GEN_PRIV_STACKS
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_current->arch.priv_stack_start =
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_current->arch.priv_stack_start =
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(ulong_t)z_priv_stack_find(_current->stack_obj);
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#else
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_current->arch.priv_stack_start =
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_current->arch.priv_stack_start =
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(ulong_t)(_current->stack_obj) +
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Z_RISCV_STACK_GUARD_SIZE;
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#endif /* CONFIG_GEN_PRIV_STACKS */
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top_of_priv_stack = Z_STACK_PTR_ALIGN(_current->arch.priv_stack_start
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+ CONFIG_PRIVILEGED_STACK_SIZE);
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top_of_user_stack = Z_STACK_PTR_ALIGN(
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_current->stack_info.start +
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_current->stack_info.size -
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_current->stack_info.delta);
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/* Set next CPU status to user mode */
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status = csr_read(mstatus);
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/* Set next CPU status to user mode */
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status = INSERT_FIELD(status, MSTATUS_MPP, PRV_U);
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status = INSERT_FIELD(status, MSTATUS_MPRV, 0);
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/* Enable IRQs for user mode */
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status = INSERT_FIELD(status, MSTATUS_MPIE, 1);
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/* Disable IRQs for m-mode until the mode switch */
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status = INSERT_FIELD(status, MSTATUS_MIE, 0);
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csr_write(mstatus, status);
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csr_write(mepc, z_thread_entry_wrapper);
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csr_write(mepc, z_thread_entry);
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/* exception stack has to be in mscratch */
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csr_write(mscratch, top_of_priv_stack);
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/* Set up Physical Memory Protection */
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#if defined(CONFIG_PMP_STACK_GUARD)
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@ -257,32 +246,16 @@ FUNC_NORETURN void z_riscv_user_mode_enter_syscall(k_thread_entry_t user_entry,
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is_user_mode = true;
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__asm__ volatile ("mv a0, %1"
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: "=r" (user_entry)
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: "r" (user_entry)
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: "memory");
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register void *a0 __asm__("a0") = user_entry;
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register void *a1 __asm__("a1") = p1;
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register void *a2 __asm__("a2") = p2;
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register void *a3 __asm__("a3") = p3;
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__asm__ volatile ("mv a1, %1"
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: "=r" (p1)
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: "r" (p1)
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: "memory");
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__asm__ volatile ("mv a2, %1"
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: "=r" (p2)
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: "r" (p2)
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: "memory");
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__asm__ volatile ("mv a3, %1"
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: "=r" (p3)
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: "r" (p3)
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: "memory");
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__asm__ volatile ("mv sp, %1"
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: "=r" (top_of_user_stack)
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: "r" (top_of_user_stack)
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: "memory");
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__asm__ volatile ("mret");
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__asm__ volatile (
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"mv sp, %4; mret"
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:
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: "r" (a0), "r" (a1), "r" (a2), "r" (a3), "r" (top_of_user_stack)
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: "memory");
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CODE_UNREACHABLE;
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}
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