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boards: arm: Enable flash for storage on mimxrt595_evk

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- The MX25UM51345G flash is connected to FLEXSPI PortA for
  mimxrt595_evk.
- Updated flexspi_mx25um51345g driver to support DTR OPI mode.
- Tested with tests/drivers/flash.

Signed-off-by: Chay Guo <changyi.guo@nxp.com>
This commit is contained in:
Chay Guo 2022-05-17 15:53:59 +08:00 • committed by Carles Cufí
commit a4c9e13ea8
12 changed files with 134 additions and 20 deletions
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19
drivers/flash/Kconfig.mcux
View file

@ -52,6 +52,25 @@ config FLASH_MCUX_FLEXSPI_HYPERFLASH
endmenu
if FLASH_MCUX_FLEXSPI_MX25UM51345G
choice FLASH_MCUX_FLEXSPI_MX25UM51345G_OPI_MODE
prompt "FlexSPI MX25UM51345G OPI mode"
default FLASH_MCUX_FLEXSPI_MX25UM51345G_OPI_DTR
help
Select the MX25UM51345G octal flash operation mode(Octal I/O STR
or Octal I/O DTR).
config FLASH_MCUX_FLEXSPI_MX25UM51345G_OPI_STR
bool "STR"
config FLASH_MCUX_FLEXSPI_MX25UM51345G_OPI_DTR
bool "DTR"
endchoice
endif # FLASH_MCUX_FLEXSPI_MX25UM51345G
config FLASH_MCUX_FLEXSPI_NOR_WRITE_BUFFER
bool "MCUX FlexSPI NOR write RAM buffer"
default y

76
drivers/flash/flash_mcux_flexspi_mx25um51345g.c
View file

@ -36,6 +36,13 @@ static uint8_t nor_write_buf[SPI_NOR_PAGE_SIZE];
read-while-write hazards. This configuration is not recommended."
#endif
/* FLASH_ENABLE_OCTAL_CMD: (01 = STR OPI Enable) , (02 = DTR OPI Enable) */
#if CONFIG_FLASH_MCUX_FLEXSPI_MX25UM51345G_OPI_DTR
#define NOR_FLASH_ENABLE_OCTAL_CMD 0x2
#else
#define NOR_FLASH_ENABLE_OCTAL_CMD 0x1
#endif
LOG_MODULE_REGISTER(flash_flexspi_nor, CONFIG_FLASH_LOG_LEVEL);
enum {
@ -71,6 +78,19 @@ static const uint32_t flash_flexspi_nor_lut[][4] = {
kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0),
},
[WRITE_ENABLE] = {
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x06,
kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
},
[ENTER_OPI] = {
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x72,
kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x20),
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x04,
kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
},
#if (NOR_FLASH_ENABLE_OCTAL_CMD == 0x1)
[READ_STATUS_REG] = {
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0x05,
kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0xFA),
@ -79,12 +99,6 @@ static const uint32_t flash_flexspi_nor_lut[][4] = {
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_SDR, kFLEXSPI_8PAD, 0x04,
kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0),
},
[WRITE_ENABLE] = {
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x06,
kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
},
[WRITE_ENABLE_OPI] = {
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0x06,
kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0xF9),
@ -117,14 +131,48 @@ static const uint32_t flash_flexspi_nor_lut[][4] = {
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_8PAD, 0x20,
kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_8PAD, 0x04),
},
[ENTER_OPI] = {
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x72,
kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x20),
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x04,
kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
#else
[READ_STATUS_REG] = {
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05,
kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xFA),
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20,
kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x4),
},
[WRITE_ENABLE_OPI] = {
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x06,
kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xF9),
},
[ERASE_SECTOR] = {
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x21,
kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xDE),
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20,
kFLEXSPI_Command_STOP, kFLEXSPI_8PAD, 0),
},
[ERASE_CHIP] = {
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x60,
kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0x9F),
},
[READ] = {
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xEE,
kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x11),
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20,
kFLEXSPI_Command_DUMMY_DDR, kFLEXSPI_8PAD, 0x08),
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04,
kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0),
},
[PAGE_PROGRAM] = {
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x12,
kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xED),
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20,
kFLEXSPI_Command_WRITE_DDR, kFLEXSPI_8PAD, 0x04),
},
#endif
};
static int flash_flexspi_nor_get_vendor_id(const struct device *dev,
@ -294,8 +342,8 @@ static int flash_flexspi_nor_wait_bus_busy(const struct device *dev)
static int flash_flexspi_enable_octal_mode(const struct device *dev)
{
struct flash_flexspi_nor_data *data = dev->data;
/* FLASH_ENABLE_OCTAL_CMD: (01 = STR OPI Enable) */
uint32_t status = 0x01;
/* FLASH_ENABLE_OCTAL_CMD: (01 = STR OPI Enable, 02 = DTR OPI Enable) */
uint32_t status = NOR_FLASH_ENABLE_OCTAL_CMD;
flash_flexspi_nor_write_enable(dev, false);
flash_flexspi_nor_write_status(dev, &status);

2
drivers/memc/memc_mcux_flexspi.c
View file

@ -178,7 +178,7 @@ static int memc_flexspi_init(const struct device *dev)
#define MEMC_FLEXSPI_CFG_XIP(node_id) DT_SAME_NODE(node_id, DT_NODELABEL(flexspi))
#elif defined(CONFIG_XIP) && defined(CONFIG_CODE_FLEXSPI2)
#define MEMC_FLEXSPI_CFG_XIP(node_id) DT_SAME_NODE(node_id, DT_NODELABEL(flexspi2))
#elif defined(CONFIG_SOC_SERIES_IMX_RT6XX)
#elif defined(CONFIG_SOC_SERIES_IMX_RT6XX) || defined(CONFIG_SOC_SERIES_IMX_RT5XX)
#define MEMC_FLEXSPI_CFG_XIP(node_id) IS_ENABLED(CONFIG_XIP)
#else
#define MEMC_FLEXSPI_CFG_XIP(node_id) false