drivers: update DCNANO LCDIF IP to use shared LCDIF binding
Update DCNANO LCDIF IP to use shared lcd interface binding. This requires changes to the RT5xx SOC and RT595 EVK, as this SOC uses the LCDIF IP, and configures the clock for it based off the new pixel-clock property. Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commit is contained in:
Daniel DeGrasse
Carles Cufí
parent
eed6e893cd
commit
a4afa7d164
5 changed files with 64 additions and 122 deletions
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@ -10,6 +10,8 @@
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#include "mimxrt595_evk_cm33-pinctrl.dtsi"
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#include <zephyr/dt-bindings/display/panel.h>
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/ {
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model = "NXP MIMXRT595-EVK board";
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compatible = "nxp,mimxrt595";
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@ -157,17 +159,28 @@
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status = "okay";
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width = <720>;
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height = <1280>;
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clk-div = <7>;
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polarity = <12>;
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hsync = <8>;
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hfp = <32>;
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hbp = <32>;
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vsync = <2>;
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vfp = <16>;
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vbp = <14>;
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display-timings {
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compatible = "zephyr,panel-timing";
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hsync-len = <8>;
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hfront-porch = <32>;
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hback-porch = <32>;
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vsync-len = <2>;
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vfront-porch = <16>;
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vback-porch = <14>;
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hsync-active = <0>;
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vsync-active = <0>;
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de-active = <1>;
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pixelclk-active = <1>;
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/*
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* Pixel clock is given by the following formula:
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* (height + vsync-len + vfront-porch + vback-porch) *
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* (width + hsync-len + hfront-porch + hback-porch) * frame rate
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*/
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clock-frequency = <62346240>;
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};
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backlight-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
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data-bus-width = "24-bit";
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pixel-format = "rgb-565";
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pixel-format = <PANEL_PIXEL_FORMAT_BGR_565>;
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};
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&mipi_dsi {
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@ -211,6 +211,12 @@ static int mcux_dcnano_lcdif_init(const struct device *dev)
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return ret;
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}
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/* Convert pixel format from devicetree to the format used by HAL */
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ret = mcux_dcnano_lcdif_set_pixel_format(dev, data->fb_config.format);
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if (ret) {
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return ret;
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}
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LCDIF_Init(config->base);
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LCDIF_DpiModeSetConfig(config->base, 0, &config->dpi_config);
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@ -242,11 +248,8 @@ static const struct display_driver_api mcux_dcnano_lcdif_api = {
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.get_framebuffer = mcux_dcnano_lcdif_get_framebuffer,
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};
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/* This macro evaluates to 4 when the pixel format enum is set to 4,
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* and 2 for all other enum values.
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*/
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#define MCUX_DCNANO_LCDIF_PIXEL_BYTES(n) \
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(((DT_INST_ENUM_IDX(n, pixel_format) / 4) * 2) + 2)
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(DISPLAY_BITS_PER_PIXEL(DT_INST_PROP(n, pixel_format)) / 8)
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/* When using external framebuffer mem, we should not allocate framebuffers
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* in SRAM. Instead, we use external framebuffer address and size
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@ -284,7 +287,7 @@ static const struct display_driver_api mcux_dcnano_lcdif_api = {
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.fb_config = { \
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.enable = true, \
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.enableGamma = false, \
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.format = DT_INST_ENUM_IDX(n, pixel_format), \
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.format = DT_INST_PROP(n, pixel_format), \
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}, \
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.pixel_bytes = MCUX_DCNANO_LCDIF_PIXEL_BYTES(n), \
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}; \
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@ -295,13 +298,24 @@ static const struct display_driver_api mcux_dcnano_lcdif_api = {
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.dpi_config = { \
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.panelWidth = DT_INST_PROP(n, width), \
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.panelHeight = DT_INST_PROP(n, height), \
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.hsw = DT_INST_PROP(n, hsync), \
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.hfp = DT_INST_PROP(n, hfp), \
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.hbp = DT_INST_PROP(n, hbp), \
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.vsw = DT_INST_PROP(n, vsync), \
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.vfp = DT_INST_PROP(n, vfp), \
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.vbp = DT_INST_PROP(n, vbp), \
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.polarityFlags = DT_INST_PROP(n, polarity), \
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.hsw = DT_INST_PROP(n, hsync_len), \
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.hfp = DT_INST_PROP(n, hfront_porch), \
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.hbp = DT_INST_PROP(n, hback_porch), \
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.vsw = DT_INST_PROP(n, vsync_len), \
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.vfp = DT_INST_PROP(n, vfront_porch), \
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.vbp = DT_INST_PROP(n, vback_porch), \
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.polarityFlags = (DT_INST_PROP(n, de_active) ? \
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kLCDIF_DataEnableActiveHigh : \
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kLCDIF_DataEnableActiveLow) | \
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(DT_INST_PROP(n, pixelclk_active) ? \
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kLCDIF_DriveDataOnRisingClkEdge : \
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kLCDIF_DriveDataOnFallingClkEdge) | \
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(DT_INST_PROP(n, hsync_active) ? \
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kLCDIF_HsyncActiveHigh : \
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kLCDIF_HsyncActiveLow) | \
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(DT_INST_PROP(n, vsync_active) ? \
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kLCDIF_VsyncActiveHigh : \
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kLCDIF_VsyncActiveLow), \
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.format = DT_INST_ENUM_IDX(n, data_bus_width), \
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}, \
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.fb_ptr = MCUX_DCNANO_LCDIF_FRAMEBUFFER(n), \
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@ -210,13 +210,17 @@ static int mcux_mipi_dsi_init(const struct device *dev)
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.bllpMode = DT_INST_ENUM_IDX(id, dpi_bllp_mode), \
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.pixelPayloadSize = DT_INST_PROP_BY_PHANDLE(id, nxp_lcdif, width), \
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.panelHeight = DT_INST_PROP_BY_PHANDLE(id, nxp_lcdif, height), \
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.polarityFlags = DT_INST_PROP_BY_PHANDLE_IDX( \
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id, nxp_lcdif, id, polarity) & 0x3, \
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.hfp = DT_INST_PROP_BY_PHANDLE(id, nxp_lcdif, hfp), \
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.hbp = DT_INST_PROP_BY_PHANDLE(id, nxp_lcdif, hbp), \
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.hsw = DT_INST_PROP_BY_PHANDLE(id, nxp_lcdif, hsync), \
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.vfp = DT_INST_PROP_BY_PHANDLE(id, nxp_lcdif, vfp), \
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.vbp = DT_INST_PROP_BY_PHANDLE(id, nxp_lcdif, vbp), \
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.polarityFlags = (DT_INST_PROP_BY_PHANDLE(id, nxp_lcdif, vsync_active) ?\
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kDSI_DpiVsyncActiveHigh : \
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kDSI_DpiVsyncActiveLow) | \
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(DT_INST_PROP_BY_PHANDLE(id, nxp_lcdif, hsync_active) ? \
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kDSI_DpiHsyncActiveHigh : \
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kDSI_DpiHsyncActiveLow), \
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.hfp = DT_INST_PROP_BY_PHANDLE(id, nxp_lcdif, hfront_porch), \
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.hbp = DT_INST_PROP_BY_PHANDLE(id, nxp_lcdif, hback_porch), \
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.hsw = DT_INST_PROP_BY_PHANDLE(id, nxp_lcdif, hsync_len), \
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.vfp = DT_INST_PROP_BY_PHANDLE(id, nxp_lcdif, vfront_porch), \
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.vbp = DT_INST_PROP_BY_PHANDLE(id, nxp_lcdif, vback_porch), \
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}, \
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.auto_insert_eotp = DT_INST_PROP(id, autoinsert_eotp), \
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.dphy_ref_freq = DT_INST_PROP_OR(id, dphy_ref_frequency, 0), \
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@ -5,7 +5,7 @@ description: NXP DCNano LCDIF (LCD Interface) controller
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compatible: "nxp,dcnano-lcdif"
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include: [display-controller.yaml, pinctrl-device.yaml]
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include: [panel-controller.yaml, pinctrl-device.yaml]
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properties:
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reg:
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@ -14,53 +14,12 @@ properties:
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interrupts:
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required: true
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clk-div:
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type: int
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required: true
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description: |
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Clock divider for LCDIF. This should be used to set the pixel clock
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based on the root clock provided to the module.
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The clock should follow the following formula:
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(display height + VSYNC pulse width + vertical front porch + vertical back porch) *
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(display width + HSYNC pulse width + horizontal front porch + horizontal back porch) *
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frame rate
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backlight-gpios:
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type: phandle-array
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required: true
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description:
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LCB backlight control gpio. Driver will initialize this GPIO to active high
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hsync:
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type: int
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required: true
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description: HSYNC pulse width in display clock cycles
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hfp:
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type: int
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required: true
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description: Horizontal front porch in display clock cycles
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hbp:
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type: int
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required: true
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description: Horizontal back porch in display clock cycles
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vsync:
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type: int
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required: true
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description: VSYNC pulse width in display clock cycles
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vfp:
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type: int
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required: true
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description: Vertical front porch in display clock cycles
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vbp:
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type: int
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required: true
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description: Vertical back porch in display clock cycles
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data-bus-width:
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type: string
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default: "24-bit"
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@ -73,54 +32,3 @@ properties:
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- "24-bit" # 24 Bit
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description:
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LCD data bus width. The default is set to the reset value of 24-bit
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pixel-format:
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type: string
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required: true
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enum:
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- "unused"
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- "xrgb-4444" # XRGB4444, 16-bit each pixel, 4-bit each element. R4G4B4 in reference manual.
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- "xrgb-1555" # XRGB1555, 16-bit each pixel, 5-bit each element. R5G5B5 in reference manual.
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- "rgb-565" # RGB565, 16-bit each pixel. R5G6B5 in reference manual.
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- "xrgb-8888" # XRGB8888, 32-bit each pixel, 8-bit each element. R8G8B8 in reference manual.
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description:
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Display pixel format.
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polarity:
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type: int
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required: true
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enum:
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- 0
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- 1
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- 2
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- 3
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- 4
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- 5
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- 6
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- 7
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- 8
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- 9
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- 10
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- 11
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- 12
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- 13
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- 14
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- 15
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description:
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OR'ed value of lcdif_polarity_flags, used to control the signal polarity.
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0000 VSYNC active low, HSYNC active low, DE active low, Drive data on falling edge.
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0001 VSYNC active high, HSYNC active low, DE active low, Drive data on falling edge.
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0010 VSYNC active low, HSYNC active high, DE active low, Drive data on falling edge.
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0011 VSYNC active high, HSYNC active high, DE active low, Drive data on falling edge.
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0100 VSYNC active low, HSYNC active low, DE active high, Drive data on falling edge.
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0101 VSYNC active high, HSYNC active low, DE active high, Drive data on falling edge.
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0110 VSYNC active low, HSYNC active high, DE active high, Drive data on falling edge.
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0111 VSYNC active high, HSYNC active high, DE active high, Drive data on falling edge.
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1000 VSYNC active low, HSYNC active low, DE active low, Drive data on rising edge.
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1001 VSYNC active high, HSYNC active low, DE active low, Drive data on rising edge.
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1010 VSYNC active low, HSYNC active high, DE active low, Drive data on rising edge.
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1011 VSYNC active high, HSYNC active high, DE active low, Drive data on rising edge.
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1100 VSYNC active low, HSYNC active low, DE active high, Drive data on rising edge.
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1101 VSYNC active high, HSYNC active low, DE active high, Drive data on rising edge.
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1110 VSYNC active low, HSYNC active high, DE active high, Drive data on rising edge.
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1111 VSYNC active high, HSYNC active high, DE active high, Drive data on rising edge.
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@ -312,9 +312,12 @@ static void clock_init(void)
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* (height + VSW + VFP + VBP) * (width + HSW + HFP + HBP) * frame rate.
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* this means the clock divider will vary depending on
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* the attached display.
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*
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* The root clock used here is the AUX0 PLL (PLL0 PFD2).
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*/
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CLOCK_SetClkDiv(kCLOCK_DivDcPixelClk,
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DT_PROP(DT_NODELABEL(lcdif), clk_div));
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((CLOCK_GetSysPfdFreq(kCLOCK_Pfd2) /
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DT_PROP(DT_NODELABEL(lcdif), clock_frequency)) + 1));
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CLOCK_EnableClock(kCLOCK_DisplayCtrl);
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RESET_ClearPeripheralReset(kDISP_CTRL_RST_SHIFT_RSTn);
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