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x86: Rework rework x86 related code to use new DTS macros

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Replace DT_PHYS_RAM_ADDR and DT_RAM_SIZE with DT_REG_ADDR/DT_REG_SIZE
for the DT_CHOSEN(zephyr_sram) node.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala 2020-04-28 10:22:19 -05:00 • committed by Kumar Gala
commit a45ea3806f
5 changed files with 29 additions and 27 deletions
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4
arch/x86/core/memmap.c
View file

@ -35,8 +35,8 @@ __weak enum x86_memmap_source x86_memmap_source = X86_MEMMAP_SOURCE_DEFAULT;
__weak struct x86_memmap_entry x86_memmap[CONFIG_X86_MEMMAP_ENTRIES] = {
{
DT_PHYS_RAM_ADDR,
DT_RAM_SIZE * 1024ULL,
DT_REG_ADDR(DT_CHOSEN(zephyr_sram)),
DT_REG_SIZE(DT_CHOSEN(zephyr_sram)),
X86_MEMMAP_ENTRY_RAM
}
};

21
arch/x86/core/x86_mmu.c
View file

@ -15,10 +15,13 @@
#include <logging/log.h>
LOG_MODULE_DECLARE(os);
#define PHYS_RAM_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_sram))
#define PHYS_RAM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_sram))
/* Despite our use of PAE page tables, we do not (and will never) actually
* support PAE. Use a 64-bit x86 target if you have that much RAM.
*/
BUILD_ASSERT(DT_PHYS_RAM_ADDR + (DT_RAM_SIZE * 1024ULL) - 1ULL <=
BUILD_ASSERT(PHYS_RAM_ADDR + PHYS_RAM_SIZE - 1ULL <=
(unsigned long long)UINTPTR_MAX);
/* Common regions for all x86 processors.
@ -665,10 +668,10 @@ static inline bool is_within_system_ram(uintptr_t addr)
{
#ifdef CONFIG_X86_64
/* FIXME: locore not included in CONFIG_SRAM_BASE_ADDRESS */
return addr < (DT_PHYS_RAM_ADDR + (DT_RAM_SIZE * 1024U));
return addr < (PHYS_RAM_ADDR + PHYS_RAM_SIZE);
#else
return (addr >= DT_PHYS_RAM_ADDR) &&
(addr < (DT_PHYS_RAM_ADDR + (DT_RAM_SIZE * 1024U)));
return (addr >= PHYS_RAM_ADDR) &&
(addr < (PHYS_RAM_ADDR + PHYS_RAM_SIZE));
#endif
}
@ -1069,15 +1072,15 @@ static void apply_mem_partition(struct x86_page_tables *ptables,
mask = K_MEM_PARTITION_PERM_MASK;
}
__ASSERT(partition->start >= DT_PHYS_RAM_ADDR,
__ASSERT(partition->start >= PHYS_RAM_ADDR,
"region at %08lx[%zu] extends below system ram start 0x%08x",
partition->start, partition->size, DT_PHYS_RAM_ADDR);
partition->start, partition->size, PHYS_RAM_ADDR);
__ASSERT(((partition->start + partition->size) <=
(DT_PHYS_RAM_ADDR + (DT_RAM_SIZE * 1024U))),
"region at %08lx[%zu] end at %08lx extends beyond system ram end 0x%08x",
(PHYS_RAM_ADDR + PHYS_RAM_SIZE)),
"region at %08lx[%zu] end at %08lx extends beyond system ram end 0x%08lx",
partition->start, partition->size,
partition->start + partition->size,
(DT_PHYS_RAM_ADDR + (DT_RAM_SIZE * 1024U)));
((uintptr_t)PHYS_RAM_ADDR) + (size_t)PHYS_RAM_SIZE);
z_x86_mmu_set_flags(ptables, (void *)partition->start, partition->size,
x86_attr, mask, false);

18
include/arch/x86/thread_stack.h
View file

@ -52,12 +52,14 @@
* many pages we need.
*/
#define PHYS_RAM_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_sram))
#define PHYS_RAM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_sram))
/* Define a range [Z_X86_PT_START, Z_X86_PT_END) which is the memory range
* covered by all the page tables needed for system RAM
*/
#define Z_X86_PT_START ((uintptr_t)ROUND_DOWN(DT_PHYS_RAM_ADDR, Z_X86_PT_AREA))
#define Z_X86_PT_END ((uintptr_t)ROUND_UP(DT_PHYS_RAM_ADDR + \
(DT_RAM_SIZE * 1024UL), \
#define Z_X86_PT_START ((uintptr_t)ROUND_DOWN(PHYS_RAM_ADDR, Z_X86_PT_AREA))
#define Z_X86_PT_END ((uintptr_t)ROUND_UP(PHYS_RAM_ADDR + PHYS_RAM_SIZE, \
Z_X86_PT_AREA))
/* Number of page tables needed to cover system RAM. Depends on the specific
@ -68,9 +70,8 @@
/* Same semantics as above, but for the page directories needed to cover
* system RAM.
*/
#define Z_X86_PD_START ((uintptr_t)ROUND_DOWN(DT_PHYS_RAM_ADDR, Z_X86_PD_AREA))
#define Z_X86_PD_END ((uintptr_t)ROUND_UP(DT_PHYS_RAM_ADDR + \
(DT_RAM_SIZE * 1024UL), \
#define Z_X86_PD_START ((uintptr_t)ROUND_DOWN(PHYS_RAM_ADDR, Z_X86_PD_AREA))
#define Z_X86_PD_END ((uintptr_t)ROUND_UP(PHYS_RAM_ADDR + PHYS_RAM_SIZE, \
Z_X86_PD_AREA))
/* Number of page directories needed to cover system RAM. Depends on the
* specific bounds of system RAM, but roughly 1 page directory per 1GB of RAM
@ -81,10 +82,9 @@
/* Same semantics as above, but for the page directory pointer tables needed
* to cover system RAM. On 32-bit there is just one 4-entry PDPT.
*/
#define Z_X86_PDPT_START ((uintptr_t)ROUND_DOWN(DT_PHYS_RAM_ADDR, \
#define Z_X86_PDPT_START ((uintptr_t)ROUND_DOWN(PHYS_RAM_ADDR, \
Z_X86_PDPT_AREA))
#define Z_X86_PDPT_END ((uintptr_t)ROUND_UP(DT_PHYS_RAM_ADDR + \
(DT_RAM_SIZE * 1024UL), \
#define Z_X86_PDPT_END ((uintptr_t)ROUND_UP(PHYS_RAM_ADDR + PHYS_RAM_SIZE, \
Z_X86_PDPT_AREA))
/* Number of PDPTs needed to cover system RAM. Depends on the
* specific bounds of system RAM, but roughly 1 PDPT per 512GB of RAM

6
lib/libc/newlib/libc-hooks.c
View file

@ -36,8 +36,10 @@ MALLOC_BSS static unsigned char __aligned(CONFIG_NEWLIB_LIBC_ALIGNED_HEAP_SIZE)
#define USED_RAM_END_ADDR POINTER_TO_UINT(&_end)
#if CONFIG_X86
#define USED_RAM_SIZE (USED_RAM_END_ADDR - DT_PHYS_RAM_ADDR)
#define MAX_HEAP_SIZE ((KB(DT_RAM_SIZE)) - USED_RAM_SIZE)
#define PHYS_RAM_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_sram))
#define PHYS_RAM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_sram))
#define USED_RAM_SIZE (USED_RAM_END_ADDR - PHYS_RAM_ADDR)
#define MAX_HEAP_SIZE (PHYS_RAM_SIZE - USED_RAM_SIZE)
#elif CONFIG_NIOS2
#include <layout.h>
#define USED_RAM_SIZE (USED_RAM_END_ADDR - _RAM_ADDR)

7
subsys/tracing/sysview/sysview_config.c
View file

@ -21,11 +21,8 @@ void SEGGER_SYSVIEW_Conf(void)
SEGGER_SYSVIEW_Init(sys_clock_hw_cycles_per_sec(),
sys_clock_hw_cycles_per_sec(),
&SYSVIEW_X_OS_TraceAPI, cbSendSystemDesc);
#if defined(DT_PHYS_RAM_ADDR) /* x86 */
SEGGER_SYSVIEW_SetRAMBase(DT_PHYS_RAM_ADDR);
#elif defined(CONFIG_SRAM_BASE_ADDRESS) /* arm, default */
SEGGER_SYSVIEW_SetRAMBase(CONFIG_SRAM_BASE_ADDRESS);
#if DT_HAS_NODE(DT_CHOSEN(zephyr_sram))
SEGGER_SYSVIEW_SetRAMBase(DT_REG_ADDR(DT_CHOSEN(zephyr_sram)));
#else
/* Setting RAMBase is just an optimization: this value is subtracted
* from all pointers in order to save bandwidth. It's not an error